EE 675 Advanced Microprocessors ARM – A little history

The ARM6 carry-select adder
scheme
• Compute sums of
various fields of
the word
for carry-in of zero
and carry-in of one
• Final result is
selected by using
the correct carry-in
value to control a
multiplexer
a,b[3:0]
sum[3:0] sum[7:4]
Worst case:
O(log 2 [word width]) gates long
+ +, +1 +, +1
c s s+1
mux
sum[15:8]
sum[31:16]
a,b[31:28]
EE 675 @ SDSU 31
mux
mux
Note: Be careful! Fan-out on some of these
gates is high so direct comparison with previous
schemes is not applicable.
The ARM6 ALU organization
• Not easy to merge the arithmetic and logic
functions =>a separate logic unit runs in parallel
with the adder, and multiplexor selects the output
invert A
function
logic/arithmetic
A operand latch B operand latch
XOR gates XOR gates
logic functions
result mux
zero detect
adder
invert B
C in
C
V
result
EE 675 @ SDSU 32
N
Z
16