EE 675 Advanced Microprocessors ARM – A little history

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PC behavior – Pipeline • As a consequence of pipeline, the PC (r15) needs to run ahead of current instruction • Instruction fetches the next instruction but one during their first cycle, i.e., PC points 8 bytes ahead of current instruction. • So a user using the PC in a program must account for the pipeline effects • The situation is more complex in cycles later than the first cycle. EE 675 @ SDSU 11 ARM multi-cycle LDMIA (load multiple) instruction ldmia r0,{r2,r3} sub r2,r3,r6 cmp r2,#3 Instruction delayed fetch decode ex ld r2 ex ld r3 fetch decode ex sub Decode stage occupied since ldmia must continue to remember decoded instruction fetch decode ex cmp time sub fetched at normal time but not decoded until LDMIA is finishing EE 675 @ SDSU 12 6
Control stalls: due to branches • Branches often introduce stalls (branch penalty) – Stall time may depend on whether branch is taken • May have to squash instructions that already started executing • Don’t know what to fetch until condition is evaluated EE 675 @ SDSU 13 bne foo sub r2,r3,r6 foo add r0,r1,r2 ARM pipelined branch Decision not made until the third clock cycle fetch decode ex bne fetch decode ex bne ex bne Two cycles of work thrown away if bne takes place fetch decode ex add time EE 675 @ SDSU 14 7
Page 1 and 2: EE 675 Advanced Microprocessors ARM
Page 3 and 4: Pipelining • The maximum processi
Page 5: ARM single-cycle instruction pipeli
Page 9 and 10: ARM9TDMI: 5-stage pipeline • Fetc
Page 11 and 12: STR (store register) datapath activ
Page 13 and 14: ARM datapath timing • Register re
Page 15 and 16: The ARM2 ALU logic for one result b
Page 17 and 18: ARM9 carry arbitration encoding •
Page 19 and 20: The 2-bit multiplication algorithm,
Page 21 and 22: ARM high-speed multiplier organizat
Page 23: ARM control logic structure • Thr

EE 675 Advanced Microprocessors ARM – A little history

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