EE 675 Advanced Microprocessors ARM – A little history

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Expanding the pipeline • 3-stage pipeline till ARM7 is very cost-effective • Better pipeline architectures required for better performance Ninst × CPI T = inst f • N inst is constant • So, only two options – Increase the clock rate, f clk requires more pipeline stages and simpler logic per stage – Reduce the average number of clock cycles per instruction, CPI requires instructions to occupy fewer pipeline slots and reduce the stalls in the pipeline Memory Bandwidth Bottlenecks clk EE 675 @ SDSU 15 5-stage Pipeline • Measures to take care of memory bottlenecks – Use of separate code and data memories – Increase the stages in the pipeline reduces the processor load/clock cycle • The above steps allow a RISC processor to work at a higher clock rate. • Use of separate instruction and data caches connected to a single DRAM greatly reduces core’s CPI EE 675 @ SDSU 16 8
ARM9TDMI: 5-stage pipeline • Fetch • Decode – instruction is decoded – register operands read (3 read ports) • Execute – an operand is shifted and the ALU result generated, or – address is computed • Buffer/data – data memory is accessed (load, store) • Write-back – write to register file next pc pc + 4 B, BL MOV pc SUBS pc LDR pc register write write-back EE 675 @ SDSU 17 +4 pc+ 8 LDM/ STM post- +4 index pre-index mux load/store address r15 ALU I-cache I decode register read ARM9TDMI: Data Forwarding ADD r3, r2, r1, LSL #3 ADD r5, r5, r3, LSL r2 ADD r3, r2, r1, LSL #3 ADD r8, r9, r10 ADD r5, r5, r3, LSL r2 LD r3, [r2] ADD r1, r2, r3 Data Forwarding Stall? r3 := r2 + 8 x r1 r5 := r5 + 2 r2 x r3 r3 := r2 + 8 x r1 r8 := r9 + r10 r5 := r5 + 2 r2 x r3 r3 := mem[r2] r1 := r2 + r3 next pc pc + 4 B, BL MOV pc SUBS pc LDR pc mul shift I-cache reg shift byte repl. D-cache rot/sgn ex rot/sgn ex fetch instruction decode immediate fields forwarding paths execute buffer/ data register write write-back EE 675 @ SDSU 18 +4 pc+8 LDM/ STM post- +4 index pre-index mux load/store address r15 ALU I decode register read mul shift reg shift byte repl. D-cache fetch instruction decode immediate fields forwarding paths execute buffer/ data 9
Page 1 and 2: EE 675 Advanced Microprocessors ARM
Page 3 and 4: Pipelining • The maximum processi
Page 5 and 6: ARM single-cycle instruction pipeli
Page 7: Control stalls: due to branches •
Page 11 and 12: STR (store register) datapath activ
Page 13 and 14: ARM datapath timing • Register re
Page 15 and 16: The ARM2 ALU logic for one result b
Page 17 and 18: ARM9 carry arbitration encoding •
Page 19 and 20: The 2-bit multiplication algorithm,
Page 21 and 22: ARM high-speed multiplier organizat
Page 23: ARM control logic structure • Thr

EE 675 Advanced Microprocessors ARM – A little history

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