EE 675 Advanced Microprocessors ARM – A little history

Pipeline: how it works
• All instructions occupy the datapath for one or more
adjacent cycles
• For each cycle that an instruction occupies the datapath,
it occupies the decode logic in the immediately
preceding cycle
• During the first datapath cycle each instruction issues
a fetch for the next instruction but one
• Branch instruction flush and refill the instruction
pipeline
EE 675 @ SDSU 7
ARM single-cycle instruction
pipeline
1
2
3
instruction
fetch decode execute
fetch decode execute
fetch decode execute
time
• At any time, 3 different instructions may occupy each of the 3-stages of
pipeline
• It may take three cycles to complete a single-cycle instruction. This is
said to have a three cycle latency
• Once a pipeline fills, the processor completes a single-cycle instruction
every clock cycle. Therefore the throughput is one instruction per
cycle.
EE 675 @ SDSU 8
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