Analog CMOS Integrated Circuit Design Set 2 - Courses - University ...

SM
Device Capacitances - 1
• The quadratic model determines the DC behavior of a MOS transistor.
• The capacitances associated with the devices are important when
studying the AC behavior of a device.
• There is a capacitance between any two terminals of a MOS transistor.
So there are 6 Capacitances in total.
• The Capacitance between Drain and Source is negligible (C DS=0).
• These capacitances will depend on the region of operation (Bias
values).
SM
EECE 488 – Set 2: Background
Device Capacitances - 2
• The following will be used to calculate the capacitances between
terminals:
1. Oxide Capacitance: C1 = W ⋅ L ⋅ Cox
,
ε ox
Cox
=
2. Depletion Capacitance:
3. Overlap Capacitance:
4. Junction Capacitance:
Sidewall Capacitance:
C = C
Bottom-plate Capacitance:
2
EECE 488 – Set 2: Background
SM 24
dep
t
ox
q ⋅ε
si ⋅ N
= W ⋅ L ⋅
4 ⋅ Φ
F
sub
C 3 = C4
= Cov
= W ⋅ LD
⋅ Cox
+ C
C jsw
C j
C 5
= C6
= C + C
j
jsw
fringe
C
jun
C j0
=
⎡ VR
⎤
⎢1
+ ⎥
⎣ Φ B ⎦
m
47
48