Analog CMOS Integrated Circuit Design Set 2 - Courses - University ...

EECE488: Analog CMOS Integrated Circuit Design 

SM 

Set 2: Background 

Shahriar Mirabbasi 

Department of Electrical and Computer Engineering 

University of British Columbia 

shahriar@ece.ubc.ca 

Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged. 

SM 

EECE 488 – Set 2: Background 

Overview 

1. Reading Assignments 

2. Structure of MOS Transistors 

3. Threshold Voltage 

4. Long-Channel Current Equations 

5. Regions of Operation 

6. Transconductance 

7. Second-Order Effects 

8. Short-Channel Effects 

9. MOS Layout 

10.Device Capacitances 

11.Small-signal Models 

12.Circuit Impedance 

13.Equivalent Transconductance 


SM 1 

1 

2

• Reading: 

SM 

Chapter 2 of the textbook 

Section 16.2 of the textbook 

Chapter 17 

Reading Assignments 

All the figures in the lecture notes are © Design of Analog CMOS Integrated Circuits, 

McGraw-Hill, 2001, unless otherwise noted. 

• Transistor stands for … 

SM 


Transistor 

• Transistor are semiconductor devices that can be classified as 

– Bipolar Junction Transistors (BJTs) 

– Field Effect Transistors (FETs) 

• Depletion-Mode FETs or (e.g., JFETs) 

• Enhancement-Mode FETs (e.g., MOSFETs) 


SM 2 

3 

4

SM 

Simplistic Model 

• MOS transistors have three terminals: Gate, Source, and Drain 

• The voltage of the Gate terminal determines the type of connection 

between Source and Drain (Short or Open). 

• Thus, MOS devices behave like a switch 

SM 

V G high 

V G low 

NMOS 

Device is ON 

D is shorted to S 

Device is OFF 

D & S are disconnected 


Device is OFF 

D & S are disconnected 

Device is ON 

D is shorted to S 

Physical Structure - 1 

SM 3 

PMOS 

• Source and Drain terminals are identical except that Source provides 

charge carriers, and Drain receives them. 

• MOS devices have in fact 4 terminals: 

– Source, Drain, Gate, Substrate (bulk) 

© Microelectronic Circuits, 2004 Oxford University Press 


5 

6

SM 


• Charge Carriers are electrons in NMOS devices, and holes in 

PMOS devices. 

• Electrons have a higher mobility than holes 

• So, NMOS devices are faster than PMOS devices 

• We rather to have a p-type substrate?! 


L D: Due to Side Diffusion 

Poly-silicon used instead of Metal 

for fabrication reasons 

• Actual length of the channel (L eff) is less than the length of gate 

SM 


• N-wells allow both NMOS and PMOS devices to reside on the 

same piece of die. 

• As mentioned, NMOS and PMOS devices have 4 terminals: 

Source, Drain, Gate, Substrate (bulk) 

• In order to have all PN junctions reverse-biased, substrate of 

NMOS is connected to the most negative voltage, and substrate 

of PMOS is connected to the most positive voltage. 


SM 4 

7 

8

• MOS transistor Symbols: 

SM 


electron 

• In NMOS Devices: Source ⎯⎯⎯→ 

Drain 

Current flows from Drain to Source 

• In PMOS Devices: 

hole 

Source ⎯⎯→ 

Drain 

Current flows from Source to Drain 

• Current flow determines which terminal is Source and which one 

is Drain. Equivalently, source and drain can be determined based 

on their relative voltages. 

SM 


Threshold Voltage - 1 

• Consider an NMOS: as the gate voltage is increased, the surface 

under the gate is depleted. If the gate voltage increases more, 

free electrons appear under the gate and a conductive channel is 

formed. 

(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, 

and (d) channel formation 

• As mentioned before, in NMOS devices charge carriers in the 

channel under the gate are electrons. 


SM 5 

9 

10

SM 


• Intuitively, the threshold voltage is the gate voltage that forces the 

interface (surface under the gate) to be completely depleted of charge (in 

NMOS the interface is as much n-type as the substrate is p-type) 

• Increasing gate voltage above this threshold (denoted by V TH or V t) 

induces an inversion layer (conductive channel) under the gate. 

SM 

Analytically: 

V TH = Φ MS + 2 ⋅ Φ F 

Q 

+ 

C 

Where: 

= the 




ΦMS = Built - in Potential = Φ gate − ΦSilicon 

Φ 

F 

dep 

dep 

ox 

difference between the work functions of 

the polysilicon 

gate and the silicon substrate 

= Work Function (electrostatic 

potential) 


K ⋅T 

⎛ N 

⋅ ln⎜ 

q ⎝ ni 

Q = Charge 

in the depletion region = 4 ⋅ q ⋅ε 

⋅ Φ ⋅ N 

SM 6 

= 

si 

F 

sub 

sub 

⎞ 

⎟ 

⎠ 

11 

12

SM 


• In practice, the “native” threshold value may not be suited for 

circuit design, e.g., V TH may be zero and the device may be on for 

any positive gate voltage. 

• Typically threshold voltage is adjusted by ion implantation into the 

channel surface (doping P-type material will increase V TH of 

NMOS devices). 

• When V DS is zero, there is no horizontal electric field present in the 

channel, and therefore no current between the source to the drain. 

• When V DS is more than zero, there is some horizontal electric field 

which causes a flow of electrons from source to drain. 

SM 


Long Channel Current Equations - 1 

• The voltage of the surface under the gate, V(x), depends on the 

voltages of Source and Drain. 

• If V DS is zero, V D= V S=V(x). The charge density Q d (unit C/m) is uniform. 

Q 

d 


− Q − C ⋅V 

− 

= = = 

L L 

Q = −WC 

− 

ox ( VGS 

VTH 

SM 7 

d 

Qd ( x) 

= −WCox 

( VGS 

−V 

( x) 

−VTH 

) 

) 

13 

( C WL) 

⋅ ( V −V 

) 

• If V DS is not zero, the channel is tapered, and V(x) is not constant. The 

charge density depends on x. 

ox 

L 

GS 

TH 

14

SM 


dQ dQ dx 

I Qd 

velocity 

dt dx dt 

⋅ = × = = 

• Current : 

Velocity in terms of V(x): 

dV 

velocity = μ ⋅ E , E = − 

dt 

− dV ( x) 

→ velocity = ( μ ⋅ ) 

dx 

Qd in terms of V(x): 

Qd ( x) 

= −WC 

ox ( VGS 

−V 

( x) 

−VTH 

) 

• Current in terms of V(x): 

L 

∫ I dx = ∫WC 

μ [ V 

D 

x= 

0 

dV ( x) 

= WCox 

[ VGS 

−V 

( x) 

−VTH 

] μ 

dx 

I D 

n 

V 

DS 

V = 0 

• Long-channel current equation: 

SM 

ox 

n 

GS 

−V 

( x) 

−V 

W 

1 

I D = μ nC 

ox [( VGS 

−VTH 

) VDS 

− V 

L 

2 


SM 8 

TH 

2 

DS 


] dV 


• If V DS ≤ V GS-V TH we say the device is operating in triode (or linear) region. 

• Current in Triode Region: 


] 

I = μ ⋅ C 

• Terminology: 

W 

Aspect Ratio = 

L 

Overdrive Voltage = Effective 

D 

n 

ox 

W ⎡ 

1 2 ⎤ 

⋅ ⋅ 

⎢( 

VGS 

−VTH 

) ⋅VDS 

− ⋅VDS 

L ⎣ 

2 ⎥ 

⎦ 

Voltage = V 

GS 

−V 

TH 

= V 

eff 

15 

16

If V 

SM 

DS 


• For very small V DS (deep Triode Region): 

I D can be approximated to be a linear function of V DS. 

The device resistance will be independent of V DS and will 

only depend on V eff. 

The device will behave like a variable resistor 

SM 

I 

D 

SM 

= I 


• If V DS > V GS – V TH, the transistor is in saturation (active) region, 

and the channel is pinched off. 

L' 

∫ I dx = 

D 

x= 

0 

VGS 

−VTH 

∫WC 

μ [ V 

V = 0 

ox 

1 W 

I D = μnC 

ox ( VGS 

−V 

2 L' 

n 

GS 

TH 

) 

−V 

( x) 

−V 

2 

TH 


SM 10 

] dV 

• Let’s, for now, assume that L’=L. The fact that 

L’ is not equal to L is a second-order effect 

known as channel-length modulation. 

• Since I D only depends on V GS, MOS transistors in saturation can be 

used as current sources. 

SM 


• Current Equation for NMOS: 

DS 

⎧ 

⎪0 

; if VGS 

< VTH 

( Cut − off ) 

⎪ 

⎪ 

⎪ W 

⎪μ 

n ⋅ Cox 

⋅ ⋅( 

VGS 

−VTH 

) ⋅V 

⎪ L 

= ⎨ 

⎪ W 

⎪μ 

n ⋅ Cox 

⋅ ⋅ 

⎪ L 

⎪ 

⎪ 

⎪1 

W 

2 

⋅ μ ⋅ C ⋅ ⋅ ( V −V 

) 

⎪ n ox 

GS TH 

⎩2 

L 

DS 

; if V 

1 2 

[ ( VGS 

−VTH 

) ⋅V 

DS − ⋅VDS 

] 

2 

; if V 

GS 

GS 

> V 

> V 


, V 

; if V 

TH 

TH 

, V 

GS 

DS 

DS 

V 

> V 

TH 

GS 

GS 

, V 

DS 

−V 

TH 

−V 

TH 

< V 

GS 

−V 

( Saturation ) 

19 

) ( Deep Triode) 

TH 

( Triode) 

20

I 

D 

SM 


• Current Equation for PMOS: 

= I 

SM 

SD 

⎧ 

⎪0 

; if VSG 

< VTH 

( Cut − off ) 

⎪ 

⎪ 

⎪ W 

⎪μ 

p ⋅ Cox 

⋅ ⋅( 

VSG 

− VTH 

) ⋅V 

⎪ L 

= ⎨ 

⎪ W 

⎪μ 

p ⋅ Cox 

⋅ ⋅ 

⎪ L 

⎪ 

⎪ 

⎪1 

W 

2 

⎪ 

⋅ μ p ⋅ Cox 

⋅ ⋅ ( VSG 

− VTH 

) 

⎩2 

L 

SD 

; if V 

1 2 

[ ( VSG 

− VTH 

) ⋅VSD 

− ⋅VSD 

] 

2 

; if V 


SM 11 

SG 

> V 

> V 

; if V 

TH 

, V 

SG 

, V 

SD 

V 

> V 

Regions of Operation - 1 

SG 

TH 

SD 

TH 

SG 

SG 

, V 

SD 

− V 

• Regions of Operation: 

Cut-off, triode (linear), and saturation (active or pinch-off) 



− V 

TH 

TH 

< V 

SG 

) ( Deep Triode) 

− V 

TH 

( Saturation ) 

• Once the channel is pinched off, the current through the channel is 

almost constant. As a result, the I-V curves have a very small slope in 

the pinch-off (saturation) region, indicating the large channel 

resistance. 

( Triode) 

21 

22

SM 


• The following illustrates the transition from pinch-off to triode region for 

NMOS and PMOS devices. 

• For NMOS devices: 

If V D increases (V G Const.), the device will go from Triode to Pinch-off. 

If V G increases (V D Const.), the device will go from Pinch-off to Triode. 

** In NMOS, as V DG increases the device will go from Triode to Pinch-off. 

• For PMOS devices: 

If V D decreases (V G Const.), the device will go from Triode to Pinch-off. 

If V G decreases (V D Const.), the device will go from Pinch-off to Triode. 

** In PMOS, as V GD increases the device will go from Pinch-off to Triode. 

• NMOS Regions of Operation: 

SM 




• Relative levels of the terminal voltages of the enhancement-type NMOS 

transistor for different regions of operation. 


SM 12 

23 

24

• PMOS Regions of Operation: 

SM 



• The relative levels of the terminal voltages of the enhancement-type 

PMOS transistor for different regions of operation. 

SM 



Example: 

For the following circuit assume that V TH=0.7V. 

• When is the device on? 

• What is the region of operation if the device is on? 

• Sketch the on-resistance of transistor M 1 as a function of V G. 


SM 13 

25 

26

SM 

Transconductance - 1 

• The drain current of the MOSFET in saturation region is ideally a 

function of gate-overdrive voltage (effective voltage). In reality, it is also 

a function of V DS. 

• It makes sense to define a figure of merit that indicates how well the 

device converts the voltage to current. 

• Which current are we talking about? 

• What voltage is in the designer’s control? 

• What is this figure of merit? 

• Transconductance in triode: 

SM 

g 

m 

∂I 

= 

∂V 

• Transconductance in saturation: 

D 

GS 

= Const. 



∂ ⎛ W 

g m = ⎜ μ n ⋅C 

ox ⋅ 

∂VGS 

⎝ L 

W 

= μ n ⋅ Cox 

⋅ ⋅VDS 

L 

SM 14 

V 

Example: 

Plot the transconductance of the following circuit as a function of V DS 

(assume V b is a constant voltage). 

∂ ⎛ W 

g m = ⎜ ⋅ μ n ⋅ Cox 

⋅ ⋅ ( V 

∂VGS 

⎝ 2 L 

W 

= μ n ⋅ Cox 

⋅ ⋅ ( VGS 

−VTH 

) 

L 

DS 

1 2 

⋅[ 

( VGS 

−VTH 

) ⋅VDS 

− ⋅VDS 

] 

1 2 

GS −VTH 

) 


2 

⎞ 

⎟ 

⎠ V 

DS 

⎞ 

⎟ 

⎠ V 

DS 

= Const. 

= Const. 

• Moral: Transconductance drops if the device enters the triode region. 

27 

28

SM 


• Transconductance, gm, in saturation: 

W 

g m = μ n ⋅ Cox 

⋅ ⋅ ( VGS 

−VTH 

) = 2μ 

n ⋅ C 

L 


SM 15 

ox 

W 

⋅ ⋅ I 

L 

D 

2 ⋅ I D 

= 

V −V 

• If the aspect ratio is constant: g m depends linearly on (V GS - V TH). 

Also, g m depends on square root of I D. 

• If I D is constant: g m is inversely proportional to (V GS - V TH). 

Also, g m depends on square root of the aspect ratio. 

• If the overdrive voltage is constant: g m depends linearly on I D. 

Also, g m depends linearly on the aspect ratio. 

SM 

Second-Order Effects (Body Effect) 

Substrate Voltage: 

• So far, we assumed that the bulk and source of the transistor are at the 

same voltage (V B=V S). 

• If V B >V s, then the bulk-source PN junction will be forward biased, and 

the device will not operate properly. 

• If V B

SM 

Body Effect - 2 

Example: 

Consider the circuit below (assume the transistor is in the active region): 

• If body-effect is ignored, V TH will be constant, and I 1 will only depend on 

V GS1=V in-V out. Since I 1 is constant, V in-V out remains constant. 

Vin −Vout 

−VTH 

= C = Const. 

→ Vin 

−Vout 

= VTH 

+ C = D = Conts. 

• In general, I 1 depends on V GS1- V TH =V in-V out-V TH (and with body effect 

V TH is not constant). Since I 1 is constant, V in-V out-V TH remains constant: 

Vin − Vout 

−VTH 

= C = Const. 

→ Vin 

−Vout 

= VTH 

+ C 

• As Vout increases, VSB1 increases, and as a result VTH Therefore, Vin-Vout Increases. 

increases. 

SM 

No Body Effect With Body Effect 


Body Effect - 3 

Example: 

For the following Circuit sketch the drain current of transistor M 1 when V X 

varies from -∞ to 0. Assume V TH0=0.6V, γ=0.4V 1/2 , and 2Φ F=0.7V. 


SM 16 

31 

32

SM 

Channel Length Modulation - 1 

• When a transistor is in the saturation region (V DS > V GS – V TH), 

the channel is pinched off. 

L 

• The drain current is 

1 W 

2 

ID = μnCox 

( VGS 

−VTH 

) where L' = L-ΔL 

2 L' 

• 

1 1 1 1 1 

= = ⋅ ≈ ⋅ ( 1+ 

ΔL 

) 

L' 

L − ΔL 

L 1− 

ΔL 

L L 

L 

1 1 

Assuming ΔL = λ ⋅V 

we get: ( ΔL 

1 

≈ ⋅ 1+ 

) = ⋅ ( 1+ 

λ ⋅V 

) 

L DS 

L 

DS 

L' 

L 

L 

1 W 

1 W 

2 

n ox GS TH 

n ox GS TH 

2 

• The drain current is I = μ C ( V −V 

) ≈ μ C ( V −V 

) ⋅ ( 1+ 

λ ⋅V 

) 

D 

2 L' 

2 L 

• As ID actually depends on both VGS and VDS, MOS transistors are 

not ideal current sources (why?). 

SM 



• λ represents the relative variation in effective length of the channel for a given 

increment in V DS. 

• For longer channels λ is smaller, i.e., λ ∝ 1/L 

• Transconductance: 

In Triode: 

∂I 

= 

∂V 

= Const. 

In Saturation (ignoring channel length modulation): 

In saturation with channel length modulation: 

g 

m 

W 

g m = μ n ⋅C 

ox ⋅ ⋅V 

L 

DS 

D 

GS 

V 

W 

W 2 ⋅ I D 

g m = μ n ⋅ Cox 

⋅ ⋅ ( VGS 

−VTH 

) = 2μ 

n ⋅ Cox 

⋅ ⋅ I D = 

L 

L V −V 

DS 

W 

W 

2 ⋅ I D 

g m = μ 

n ⋅ Cox 

⋅ ⋅ ( VGS 

−VTH 

) ⋅ ( 1+ 

λ ⋅VDS 

) = 2μ 

n ⋅C 

ox ⋅ ⋅ I D ⋅ ( 1+ 

λ ⋅VDS 

) = 

L 

L 

VGS 

−VTH 

• The dependence of ID on VDS is much weaker than its dependence on VGS. EECE 488 – Set 2: Background 

SM 17 

GS 

TH 

33 

34 

DS

SM 


Example: 

Given all other parameters constant, plot ID-VDS characteristic of an NMOS 

for L=L1 and L=2L1 • In Triode Region: 

• In Saturation Region: 

W 

ID 

≈ μn 

⋅Cox 

⋅ 

L 

∂ID 

W 

Therefore : ∝ 

∂VDS 

L 

1 

⋅[ 

( VGS 

−VTH 

) ⋅VDS 

− ⋅V 

2 

DS] 

1 W 

ID 

≈ μnCox 

GS TH 

2 L 

∂I 

1 W 

So we get : D = μnCox 

∂VDS 

2 L 

∂ID 

W ⋅ λ W 

Therefore : ∝ ∝ 

∂V 

L 2 

DS L 

2 

( V −V 

) ⋅ ( 1+ 

λ ⋅V 

) 


( V −V 

) 

SM 18 

GS 

DS 

2 

TH ⋅ λ 

• Changing the length of the device from L 1 to 2L 1 will flatten the I D-V DS 

curves (slope will be divided by two in triode and by four in saturation). 

• Increasing L will make a transistor a better current source, while 

degrading its current capability. 

• Increasing W will improve the current capability. 

SM 

Sub-threshold Conduction 

• If V GS < V TH, the drain current is not zero. 

• The MOS transistors behave similar to BJTs. 

• In BJT: 

• In MOS: I 

I = I ⋅ e 

C 

D 

= I 

S 

0 

⋅ e 

VBE 

VT 

VGS 

ζ ⋅VT 

• As shown in the figure, in MOS transistors, the drain current drops by 

one decade for approximately each 80mV of drop in V GS. 

• In BJT devices the current drops faster (one decade for approximately 

each 60mv of drop in V GS). 

• This current is known as sub-threshold or weak-inversion conduction. 


2 

35 

36

CMOS Processing Technology 

• Top and side views of a typical CMOS process 

SM EECE 588 – Set 1: Introduction and Background 

CMOS Processing Technology 

• Different layers comprising CMOS transistors 


SM 19 

37 

38

Photolithography (Lithography) 

• Used to transfer circuit layout information to the wafer 


SM 

Typical Fabrication Sequence 

SM 20 

39 

40

Self-Aligned Process 

• Why source and drain junctions are formed after the gate oxide 

and polysilicon layers are deposited? 


• Oxide spacers and silicide 

Back-End Processing 


SM 21 

41 

42


• Contact and metal layers fabrication 



• Large contact areas should be avoided to minimize the 

possibility of spiking 


SM 22 

43 

44

SM 

MOS Layout - 1 

• It is beneficial to have some insight into the layout of the MOS devices. 

• When laying out a design, there are many important parameters we 

need to pay attention to such as: drain and source areas, 

interconnects, and their connections to the silicon through contact 

windows. 

• Design rules determine the criteria that a circuit layout must meet for a 

given technology. Things like, minimum length of transistors, minimum 

area of contact windows, … 

SM 


MOS Layout - 2 

Example: 

Figures below show a circuit with a suggested layout. 

• The same circuit can be laid out in different ways, producing different 

electrical parameters (such as different terminal capacitances). 


SM 23 

45 

46

SM 

Device Capacitances - 1 

• The quadratic model determines the DC behavior of a MOS transistor. 

• The capacitances associated with the devices are important when 

studying the AC behavior of a device. 

• There is a capacitance between any two terminals of a MOS transistor. 

So there are 6 Capacitances in total. 

• The Capacitance between Drain and Source is negligible (C DS=0). 

• These capacitances will depend on the region of operation (Bias 

values). 

SM 



• The following will be used to calculate the capacitances between 

terminals: 

1. Oxide Capacitance: C1 = W ⋅ L ⋅ Cox 

, 

ε ox 

Cox 

= 

2. Depletion Capacitance: 

3. Overlap Capacitance: 

4. Junction Capacitance: 

Sidewall Capacitance: 

C = C 

Bottom-plate Capacitance: 

2 


SM 24 

dep 

t 

ox 

q ⋅ε 

si ⋅ N 

= W ⋅ L ⋅ 

4 ⋅ Φ 

F 

sub 

C 3 = C4 

= Cov 

= W ⋅ LD 

⋅ Cox 

+ C 

C jsw 

C j 

C 5 

= C6 

= C + C 

j 

jsw 

fringe 

C 

jun 

C j0 

= 

⎡ VR 

⎤ 

⎢1 

+ ⎥ 

⎣ Φ B ⎦ 

m 

47 

48

SM 


In Cut-off: 

1. CGS: is equal to the overlap capacitance. CGS = Cov 

= C3 

2. CGD: is equal to the overlap capacitance. CGD = Cov 

= C4 

3. CGB: is equal to Cgate-channel = C1 in series with Cchannel-bulk = C2. SM 

4. C SB: is equal to the junction capacitance between source and 

bulk. 

5. C DB: is equal to the junction capacitance between source and 

bulk. 

CSB = C5 

CDB = C6 



In Triode: 

• The channel isolates the gate from the substrate. This means that if V G 

changes, the charge of the inversion layer are supplied by the drain 

and source as long as V DS is close to zero. So, C 1 is divided between 

gate and drain terminals, and gate and source terminals, and C 2 is 

divided between bulk and drain terminals, and bulk and source 

terminals. 

1. C GS: 

2. C GD: 

C 

CGS = Cov 

+ 

1 

2 

3. CGB: the channel isolates the gate from the substrate. 

C2 

4. C C 

SB: SB = C5 

+ 

2 

5. C C2 

DB: 

C DB 

C 

= 

C + 

CGD ov 

1 

2 

= C6 

+ 

2 


SM 25 

CGB 

= 0 

49 

50

SM 


In Saturation: 

• The channel isolates the gate from the substrate. The voltage across 

the channel varies which can be accounted for by adding two 

equivalent capacitances to the source. One is between source and 

gate, and is equal to two thirds of C1. The other is between source and 

bulk, and is equal to two thirds of C2. 1. CGS: 2 

CGS = Cov 

+ C1 

3 

2. CGD: C C = 

SM 

GD 

3. CGB: the channel isolates the gate from the substrate. 

4. 

5. 

CSB: CDB: 2 

CSB = C5 

+ C2 

3 

• In summary: 

C GS 

C GD 

C GB 

C SB 

C DB 

C DB = C6 

ov 



Cut-off 

C ⋅C 

C 

Cov 


SM 26 

Triode 

C1 

Cov + 

2 

C 

Cov + 

2 

CGB 

= 0 

Saturation 

Cov + 

Cov ov C 

1 

1 2 CGB 

C1 

1 C2 

〈 〈 

+ 

C5 

C6 

0 

C2 

C 5 + 

2 

C2 

C 6 + 

2 

0 

2 

C1 

3 

2 

C 5 + C 

3 

C6 

2 

51 

52

Importance of Layout 

Example (Folded Structure): 

Calculate the gate resistance of the circuits shown below. 

Folded structure: 

• Decreases the drain capacitance 

• Decreases the gate resistance 

• Keeps the aspect ratio the same 


• Resistors 

Passive Devices 


SM 27 

53 

54

• Capacitors: 


• Capacitors 




SM 28 

55 

56

• Inductors 



Latch-Up 

• Due to parasitic bipolar transistors in a CMOS process 


SM 29 

57 

58

SM 

Small Signal Models - 1 

• Small signal model is an approximation of the large-signal model 

around the operation point. 

• In analog circuits most MOS transistors are biased in saturation region. 

• In general, I D is a function of V GS, V DS, and V BS. We can use this Taylor 

series approximation: 

SM 

D 

D 

D 

Taylor Expansion : I D = I D0 

+ ⋅ ΔVGS 

+ ⋅ ΔVDS 

+ ⋅ ΔVBS 

+ second order terms 

∂VGS 

∂VDS 

∂VBS 

ΔI 

D 

∂I 

≈ 

∂V 

D 

GS 

⋅ ΔV 

GS 

∂I 

+ 

∂V 

D 

DS 

• Current in Saturation: 

• Taylor approximation: 

• Partial Derivatives: 

∂I 

∂V 

∂I 

∂V 

∂I 

∂V 

D 

GS 

D 

DS 

D 

BS 

= μ ⋅ C 

n 

∂I 

= 

∂V 

g 

D 

TH 

m 

ox 

1 

= ⋅ μ n ⋅ C 

2 

= − 

⋅ ΔV 

∂I 

DS 

∂I 

+ 

∂V 

D 

BS 

⋅ ΔV 


SM 30 

∂I 

BS 


∂I 

ΔV 

= g m ⋅ ΔVGS 

+ 

r 


W 

⋅ ⋅ ( V 

L 

ox 

∂V 

⋅ 

∂V 

TH 

BS 

⎡ 

⋅ ⎢− 

⎢ 

⎣ 

2 

GS 

o 

DS 

+ g 

mb 

⋅ ΔV 

1 W 

2 1 W 

2 

nC 

ox ( VGS 

−VTH 

) ≈ μ nCox 

GS TH 

BS 

59 

( V −V 

) ⋅ ( + V ) 

I D = μ 1 λ ⋅ 

2 L' 

2 L 

Δ 

W 

⋅ ⋅ ( V 

L 

∂I 

∂I 

∂I 

D 

D 

D 

I D ≈ ⋅ ΔVGS 

+ ⋅ ΔVDS 

+ ⋅ Δ 

∂VGS 

∂VDS 

∂VBS 

−V 

F 

GS 

TH 

−V 

⎡ 

= ⎢− 

μ n ⋅ C 

⎣ 

γ 

2 ⋅ Φ 

+ V 

) ⋅ 

SB 

ox 

( 1+ 

λ ⋅V 

) 

2 

TH 

W 

⋅ ⋅ ( V 

L 

⎤ 

⎥ = g 

⎥ 

⎦ 

m 

DS 

GS 

= g 

−V 

⋅η 

= g 

TH 

mb 

m 

1 

) ⋅ λ ≈ I D ⋅ λ = 

r 

) ⋅ 

o 

( 1+ 

λ ⋅V 

) 

DS 

V 

BS 

⎤ 

⎡ 

⎥ ⋅ ⎢− 

⎦ ⎢ 

⎣ 

2 

γ 

2 ⋅ Φ 

F 

+ V 

60 

SB 

⎤ 

⎥ 

⎥ 

⎦ 

DS

• Small-Signal Model: 

SM 


DS 

iD = g m ⋅ vGS 

+ + g mb ⋅ 

ro 

v 

• Terms, g mv GS and g mbv BS, can be modeled by dependent sources. 

These terms have the same polarity: increasing v G, has the same 

effect as increasing v B. 

• The term, v DS/r o can be modeled using a resistor as shown below. 

SM 



• Complete Small-Signal Model with Capacitances: 

• Small signal model including all the capacitance makes the intuitive 

(qualitative) analysis of even a few-transistor circuit difficult! 

• Typically, CAD tools are used for accurate circuit analysis 

• For intuitive analysis we try to find a simplest model that can represent 

the role of each transistor with reasonable accuracy. 


SM 31 

v 

BS 

61 

62

SM 

Circuit Impedance - 1 

• It is often useful to determine the impedance of a circuit seen from a 

specific pair of terminals. 

• The following is the recipe to do so: 

1. Connect a voltage source, V X, to the port. 

2. Suppress all independent sources. 

3. Measure or calculate I X. 

SM 

V 

R = X 

I 



Example: 

• Find the small-signal impedance of the following current 

sources. 

• We draw the small-signal model, which is the same for both 

circuits, and connect a voltage source as shown below: 

v 

v 

X 

X 

i = 

+ g ⋅ v = 

X 

m GS 

r 

r 

o 

vX 

R = = r 

X 

o 

i 

X 


SM 32 

X 

X 

o 

63 

64

SM 


Example: 

• Find the small-signal impedance of the following circuits. 

• We draw the small-signal model, which is the same for both 

circuits, and connect a voltage source as shown below: 

SM 

v 

v 

X 

X 

i = − g ⋅ v − g ⋅ v = + g ⋅ v + g ⋅ v 

X 

m GS mb BS 

m X mb X 

r 

r 

o 

v 1 1 1 

X R = = 

= r 

X 

o 

i 1 

g g 

X 

m mb 

+ g + g m mb 

r 

o 



Example: 

• Find the small-signal impedance of the following circuit. This 

circuit is known as the diode-connected load, and is used 

frequently in analog circuits. 

• We draw the small-signal model and connect the voltage 

source as shown below: 

v 

v 

⎛ 1 ⎞ 

X 

X 

i = + g ⋅ v = + g ⋅ v = v ⋅⎜ 

+ g ⎟ 

X 

m GS 

m X X 

m 

r 

r 

r 

o 

o 

⎝ o ⎠ 

v 1 1 

X R = = = r 

X 

o 

i 1 g 

X 

m + gm 

r 

o 

• If channel length modulation is ignored (r o=∞) we get: 

1 

R = 

r = ∞ 

X o 

g 

m 

1 1 

= 

g g 

m 

m 


SM 33 

o 

65 

66

SM 


Example: 

• Find the small-signal impedance of the following circuit. This 

circuit is a diode-connected load with body effect. 

v 

v 

X 

X 

i = − g ⋅ v − g ⋅ v = + g ⋅ v + g ⋅ v 

X 

m GS mb BS 

m X mb X 

r 

r 

o 

⎛ 1 ⎞ 

= v ⋅⎜ 

+ g + g ⎟ 

X 

m mb 

⎝ ro 

⎠ 

v 1 

1 1 1 

X R = = 

= r = r 

X 

o 

o 

i 1 

g g g g 

X 

m mb 

m mb 

+ g + g 

+ 

m mb 

r 

o 

o 

• If channel length modulation is ignored (r o=∞) we get: 

1 

R = r = ∞ 

X o 

g + g 

SM 

m 

mb 

1 1 1 1 

= = 

g + g g + g g g 

m 

mb 

m 

mb 


Equivalent Transconductance - 1 

• Recall that the transconductance of a transistor was a a figure of 

merit that indicates how well the device converts a voltage to current. 

∂I 

D g = m 

∂V 

GS 

V 

DS 

• It is sometimes useful to define the equivalent transconductance of a 

circuit as follows: 

∂I 

OUT G = m 

∂V 

V = Const. 

IN 

OUT 

SM 34 

m 

mb 

= Const. 

• The following is a small-signal block diagram of an arbitrary circuit 

with a Norton equivalent at the output port. We notice that: 

V OUT=Constant so v OUT=0 in the small signal model. 

i 

G 

= m 

v 

OUT 

IN 

v 

OUT 

= 0 


67 

68

SM 


Example: 

• Find the equivalent transconductance of an NMOS transistor 

in saturation from its small-signal model. 

SM 

i 

OUT 

= g ⋅ v = g ⋅ v 

m 

IN 

GS 

iOUT 

G = = g 

m 

m 

v 



Example: 

• Find the equivalent transconductance of the following circuit 

when the NMOS transistor in saturation. 

v 

i 

IN 

OUT 

= v 

GS 

+ v = v + i 

S 

GS 

OUT 

⋅ R 

⎛ 

R ⎞ S 

i ⋅⎜1 

+ g ⋅ R + g ⋅ R + ⎟ = g ⋅ v 

OUT 

m S mb S 

m IN 

⎝ 

rO 

⎠ 

i 

g 

OUT 

m 

G = = 

= 

m 

v 

R 

IN 

S r r O O 

1+ 

g ⋅ R + g ⋅ R + 

+ ⋅ 

m S mb S 

r 

O 

S 

vS 

= g ⋅ v + g ⋅ v − = g ⋅ ( 

v − i ⋅ R ) + g ⋅ 

m GS mb BS 

m IN OUT S 

mb 

r 

O 

SM 35 

m 

IN 


m 

( − i ⋅ R ) 

g ⋅ r 

O 

OUT 

OUT 

( g ⋅ R + g ⋅ R ) + R 

m S mb S 

S 

S 

i 

− 

⋅ RS 

r 

O 

69 

70

SM 

Short-Channel Effects 

• Threshold Reduction 

– Drain-induced barrier lowering (DIBL) 

• Mobility degradation 

• Velocity saturation 

• Hot carrier effects 

– Substrate current 

– Gate current 

• Output impedance variation 

SM 


Threshold Voltage Variation in Short Channel Devices 

• The Threshold of transistors fabricated on the same chip decreases as 

the channel length decreases. 

• Intuitively, the extent of depletion regions associated with drain and 

source in the channel area, reduces the immobile charge that must be 

imaged by the charge on the gate. 


SM 36 

71 

72

SM 

Drain-Induced Barrier Lowering (DIBL) 

When the channel is short, the drain 

voltage increases the channel surface 

potential, lowering the barrier to flow 

charge from source (think of increased 

electric field) and therefore, decreasing 

the threshold. 

SM 


Effects of Velocity Saturation 

• Due to drop in mobility at high electric fields 

• (a) Premature drain current saturation and (b) reduction in g m 


SM 37 

73 

74

SM 

Hot Carrier Effects 

• Short channel devices may experience high lateral drain-source 

electric field 

• Some carriers that make it to drain have high velocity (called 

“hot” carriers) 

• “Hot” carriers may “hit” silicon atoms at high speed and cause 

impact ionization 

• The resulting electron and holes are absorbed by the drain and 

substrate causing extra drain-substrate current 

• Really “hot” carriers may be injected into gate oxide and flow out 

of gate causing gate current! 

Recall the definition of λ. 

SM 


Output Impedance Variation 


SM 38 

75 

76

SM 

Output Impedance Variation in Short-Channel Devices 


SM 39 

77

Analog CMOS Integrated Circuit Design Set 2 - Courses - University ...

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