FM3 MB9B500 Series - Microcontrollers - Fujitsu

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MB9B500 Series BLOCK DIAGRAM MB9BF500 Block Diagram TRSTX,TCK TDI,TMS TDO TRACED[3:0], TRACECLK INITX X0 X1 X0A X1A AVCC, AVSS,AVRH AN[15:0] ADTG[8:0] TIOA[7:0] TIOB[7:0] AIN[1:0] BIN[1:0] ZIN[1:0] IC0[3:0] IC1[3:0] FRCK[1:0] DTTI[1:0]X RTO0[5:0] RTO1[5:0] MB9BF500 SWJ-DP ETM Code RAM TPIU ROM Table 16Kbyte Cortex-M3 Core @80MHz(Max.) I Flash I/F On-Chip Flash D Security 256Kbyte MPU NVIC Sys Dual-Timer WatchDog Timer (Software) Clock Reset Generator WatchDog Timer (Hardware) Main Osc Sub. Osc CSV CLK RST PLL CR 4MHz A/D Converter x3 10bit A/D Converter 10bit A/D Converter 10bit A/D Converter Base Timer 16-bit 8ch /32-bit 4ch QPRC 2ch A/D Activation Compare 3ch 16-bit Input Capture 4ch 16-bit FreeRun Timer 3ch 16-bit Output Compare 6ch Waveform Generator 3ch 16-bit PPG 3ch Multi Function Timer x2 CR 100KHz AHB-APB Bridge: APB0 (Max.40MHz) AHB-APB Bridge : APB1 (Max.40MHz) AHB-APB Bridge : APB2 ( Max.40MHz) Multi-layer AHB (Max.80MHz) AHB-AHB Bridge External Bus IF Regurator Ctrl USB Clock ctrl CAN Prescaler IRQ-Monitor CRC Accelerator Watch Counter External Interrupt Controller 16-pin + NMI MODE-Ctrl GPIO Multi Serial IF 8ch (with FIFO ch.4~7) *HW flow control(ch.4) PLL USB 2.0 (Host /Func) On-Chip SRAM 16Kbyte DMAC 8ch CAN CAN PHY Power On Reset Regurator + LVD Regurator + LVD PIN-Function-Ctrl USBVCC UDP0,UDM0 UHCONX TX0,RX0 TX1,RX1 MAD[24:0] MDATA[15:0] MCSX[7:0], MOEX,MWEX, MNALE, MNCLE MNWEX, MNREX, MDQM[1:0] VCC,VSS C INT[15:0] NMIX MD[1:0] P0[F:0], P1[F:0], ・・ Px[x:0], SCK[7:0] SIN[7:0] SOT[7:0] 52 DS706-00010-1v0-E CTS4 RTS4
MB9BF504/505/506 Block Diagram TRSTX,TCK TDI,TMS TDO TRACED[3:0], TRACECLK INITX X0 X1 X0A X1A AVCC, AVSS,AVRH AN[15:0] ADTG[8:0] TIOA[7:0] TIOB[7:0] AIN[1:0] BIN[1:0] ZIN[1:0] IC0[3:0] IC1[3:0] FRCK[1:0] DTTI[1:0]X RTO0[5:0] RTO1[5:0] MB9BF504/505/506 SWJ-DP Dual-Timer Clock Reset Generator WatchDog Timer (Hardware) Main Osc Sub. Osc CSV PLL CR 4MHz 12bit A/D Converter A/D Activation Compare 3ch 16-bit Input Capture 4ch 16-bit FreeRun Timer 3ch 16-bit Output Compare 6ch Waveform Generator 3ch 16-bit PPG 3ch ETM TPIU ROM Table Cortex-M3 Core @80MHz(Max.) I D MPU NVIC Sys WatchDog Timer (Software) CLK RST A/D Converter x3 12bit A/D Converter 12bit A/D Converter Base Timer 16-bit 8ch /32-bit 4ch QPRC 2ch Multi Function Timer x2 CR 100KHz AHB-APB Bridge: APB0(Max.40MHz) AHB-APB Bridge : APB1 (Max.40MHz) AHB-APB Bridge : APB2 ( Max.40MHz) Multi-layer AHB (Max.80MHz) Flash I/F Security AHB-AHB Bridge External Bus IF Regurator Ctrl USB Clock ctrl CAN Prescaler IRQ-Monitor CRC Accelerator Watch Counter External Interrupt Controller 16-pin + NMI MODE-Ctrl GPIO Multi Serial IF 8ch (with FIFO ch.4~7) *HW flow control(ch.4) MB9B500 Series Code SRAM 16/24/32 Kbyte On-Chip Flash 256/384/512 Kbyte On-Chip SRAM 16/24/32 Kbyte USB 2.0 (Host /Func) DMAC 8ch CAN CAN PHY Power On Reset Regurator + LVD Regurator + LVD PIN-Function-Ctrl Product device MB9BF504 MB9BF505 MB9BF506 On-Chip Flash 256Kbyte 384Kbyte 512Kbyte Code SRAM 16Kbyte 24Kbyte 32Kbyte On-Chip SRAM 16Kbyte 24Kbyte 32Kbyte DS706-00010-1v0-E PLL USBVCC UDP0,UDM0 UHCONX TX0,RX0 TX1,RX1 MAD[24:0] MDATA[15:0] MCSX[7:0], MOEX,MWEX, MNALE, MNCLE MNWEX, MNREX, MDQM[1:0] VCC,VSS C INT[15:0] NMIX MD[1:0] P0[F:0], P1[F:0], ・・ Px[x:0], SCK[7:0] SIN[7:0] SOT[7:0] CTS4 RTS4 53
Page 1 and 2: FUJITSU SEMICONDUCTOR DATA SHEET Co
Page 3 and 4: MB9B500 Series Multi-function Seri
Page 5 and 6: Dual Timer (Two 32/16bit Down Count
Page 7 and 8: PRODUCT LINEUP MB9B500 Series Memo
Page 9 and 10: PIN ASSIGNMENT FPT-100P-M20/M23 VS
Page 11 and 12: BGA-112P-M04 MB9B500 Series ・ Th
Page 13 and 14: Pin no. LQFP-100 BGA-112 LQFP-120 D
Page 25 and 26: MB9B500 Series SIGNAL DESCRIPTION
Page 27 and 28: MB9B500 Series The number after the
Page 41 and 42: MB9B500 Series Type Circuit Remarks
Page 43 and 44: MB9B500 Series Type Circuit Remarks
Page 45 and 46: MB9B500 Series PRECAUTIONS FOR HAN
Page 47 and 48: MB9B500 Series Precautions for Pac
Page 49 and 50: HANDLING DEVICES MB9B500 Series Po
Page 51: HANDLING MB9BF500 MB9B500 Series H
Page 55 and 56: MB9B500 Series Memory Map(2) 0x2008
Page 57 and 58: PIN STATUS IN EACH CPU STATE The te
Page 59 and 60: Pin status type Power-on reset or l
Page 61 and 62: Pin status type Function group Powe
Page 63 and 64: MB9B500 Series 2. Absolute Maximum
Page 65 and 66: DC Characteristics The following ta
Page 67 and 68: MB9B500 Series (2) MB9BF504/505/506
Page 69 and 70: MB9B500 Series 2. Pin Characteristi
Page 71 and 72: MB9B500 Series (2) Sub Clock Input
Page 73 and 74: MB9B500 Series (7) External Bus Tim
Page 75 and 76: MB9B500 Series ・ NAND FLASH mode
Page 77 and 78: (8) Base Timer Input Timing ・ Tim
Page 79 and 80: SCK SOT SIN SCK SOT SIN V IH tF DS7
Page 81 and 82: S C K S O T S IN S C K S O T S IN V
Page 83 and 84: SCK SOT SIN SCK SOT SIN *2 VOH VO L
Page 85 and 86: SCK SOT SIN SCK SOT SIN VOH VOL MB9
Page 87 and 88: MB9B500 Series (11) Quadrature Posi
Page 89 and 90: MB9B500 Series (12) I 2 C timing (V
Page 91 and 92: MB9B500 Series (14) JTAG timing (Vc
Page 93 and 94: (Continued) MB9B500 Series The outp
Page 95 and 96: MB9B500 Series ・ Setting examples
Page 97 and 98: MB9B500 Series ・ Setting examples
Page 99 and 100: ・Definition of 10-bit A/D Convert
Page 101 and 102: 12bit A/D Converter This chapter sh
Page 103 and 104:
・Definition of 12-bit A/D Convert
Page 105 and 106:
MB9B500 Series *3 : The output driv
Page 107 and 108:
(Continued) Figure 1 Low-Speed Load
Page 109 and 110:
Flash Memory Write/Erase Characteri
Page 111 and 112:
Power supply current (Sub timer mod
Page 113 and 114:
PACKAGE DIMENSIONS 100-pin plastic
Page 115 and 116:
(Continued) 120-pin plastic LQFP (F
Page 117 and 118:
MAJOR CHANGES IN THIS EDITION Page
Page 119 and 120:
DS706-00010-1v0-E MB9B500 Series 11
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FM3 MB9B500 Series - Microcontrollers - Fujitsu

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