FM3 MB9B500 Series - Microcontrollers - Fujitsu

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MB9B500 Series BIN AIN ZIN ZIN AIN/BIN tBHL tBUAU tAUBD tZABE tZHL tAHL tBDAD tBLL tADBU tALL tZLL tABEZ 88 DS706-00010-1v0-E
MB9B500 Series (12) I 2 C timing (Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40C to + 85C) Typical High-speed Parameter Symbol Conditions mode mode Unit Remarks Min Max Min Max SCL clock frequency (Repeated) START condition fSCL 0 100 0 400 kHz hold time SDA SCL tHDSTA 4.0 - 0.6 - μs SCLclock "L" width tLOW 4.7 - 1.3 - μs SCLclock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START setup time SCL SDA tSUSTA CL = 50pF, 4.7 - 0.6 - μs Data hold time SCL SDA tHDDAT R = (Vp/IOL) (*1) 0 3.45 (*2) 0 0.9 (*3) μs Data setup time SDA SCL tSUDAT 250 - 100 - ns STOP condition setup time SCL SDA Bus free time between tSUSTO 4.0 - 0.6 - μs "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs 2 tCYCP 2 tCYCP Noise filter tSP - - - ns (*4) (*4) *1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal. *3 : A high-speed mode I 2 C bus device can be used on a standard mode I 2 C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4 : tCYCP is the peripheral clock cycle time. To use I 2 C, set the peripheral bus clock at 8 MHz or more. SDA SCL tHDSTA tLOW DS706-00010-1v0-E tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSP tSUSTO tBUF 89
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FUJITSU SEMICONDUCTOR DATA SHEET Co
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MB9B500 Series Multi-function Seri
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Dual Timer (Two 32/16bit Down Count
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PRODUCT LINEUP MB9B500 Series Memo
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PIN ASSIGNMENT FPT-100P-M20/M23 VS
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BGA-112P-M04 MB9B500 Series ・ Th
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Pin no. LQFP-100 BGA-112 LQFP-120 D
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MB9B500 Series SIGNAL DESCRIPTION
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MB9B500 Series The number after the
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Page 37 and 38: MB9B500 Series The number after the
Page 39 and 40: MB9B500 Series The number after the
Page 41 and 42: MB9B500 Series Type Circuit Remarks
Page 43 and 44: MB9B500 Series Type Circuit Remarks
Page 45 and 46: MB9B500 Series PRECAUTIONS FOR HAN
Page 47 and 48: MB9B500 Series Precautions for Pac
Page 49 and 50: HANDLING DEVICES MB9B500 Series Po
Page 51 and 52: HANDLING MB9BF500 MB9B500 Series H
Page 53 and 54: MB9BF504/505/506 Block Diagram TRST
Page 55 and 56: MB9B500 Series Memory Map(2) 0x2008
Page 57 and 58: PIN STATUS IN EACH CPU STATE The te
Page 59 and 60: Pin status type Power-on reset or l
Page 61 and 62: Pin status type Function group Powe
Page 63 and 64: MB9B500 Series 2. Absolute Maximum
Page 65 and 66: DC Characteristics The following ta
Page 67 and 68: MB9B500 Series (2) MB9BF504/505/506
Page 69 and 70: MB9B500 Series 2. Pin Characteristi
Page 71 and 72: MB9B500 Series (2) Sub Clock Input
Page 73 and 74: MB9B500 Series (7) External Bus Tim
Page 75 and 76: MB9B500 Series ・ NAND FLASH mode
Page 77 and 78: (8) Base Timer Input Timing ・ Tim
Page 79 and 80: SCK SOT SIN SCK SOT SIN V IH tF DS7
Page 81 and 82: S C K S O T S IN S C K S O T S IN V
Page 83 and 84: SCK SOT SIN SCK SOT SIN *2 VOH VO L
Page 85 and 86: SCK SOT SIN SCK SOT SIN VOH VOL MB9
Page 87: MB9B500 Series (11) Quadrature Posi
Page 91 and 92: MB9B500 Series (14) JTAG timing (Vc
Page 93 and 94: (Continued) MB9B500 Series The outp
Page 95 and 96: MB9B500 Series ・ Setting examples
Page 97 and 98: MB9B500 Series ・ Setting examples
Page 99 and 100: ・Definition of 10-bit A/D Convert
Page 101 and 102: 12bit A/D Converter This chapter sh
Page 103 and 104: ・Definition of 12-bit A/D Convert
Page 105 and 106: MB9B500 Series *3 : The output driv
Page 107 and 108: (Continued) Figure 1 Low-Speed Load
Page 109 and 110: Flash Memory Write/Erase Characteri
Page 111 and 112: Power supply current (Sub timer mod
Page 113 and 114: PACKAGE DIMENSIONS 100-pin plastic
Page 115 and 116: (Continued) 120-pin plastic LQFP (F
Page 117 and 118: MAJOR CHANGES IN THIS EDITION Page
Page 119 and 120: DS706-00010-1v0-E MB9B500 Series 11
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FM3 MB9B500 Series - Microcontrollers - Fujitsu

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