FM3 MB9B500 Series - Microcontrollers - Fujitsu

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MB9B500 Series Peripheral Address Map 56 Start address End address Bus Peripherals 0x4000_0000 0x4000_1000 0x4000_0FFF 0x4000_FFFF AHB Flash I/F register Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_3000 0x4001_2FFF 0x4001_4FFF APB0 Software Watchdog timer Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_6000 0x4002_5FFF 0x4002_6FFF APB1 Base Timer Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_5FFF Low Voltage Detector 0x4003_6000 0x4003_6FFF APB2 USB clock generator 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4004_FFFF USB ch.0 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF AHB Reserved 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x4006_3FFF CAN ch.1 0x4006_4000 0x41FF_FFFF Reserved DS706-00010-1v0-E
PIN STATUS IN EACH CPU STATE The terms used for pin status have the following meanings. ・ INITX=0 This is the period when the INITX pin is the "L" level. ・ INITX=1 This is the period when the INITX pin is the "H" level. MB9B500 Series ・ SPL=0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0". ・ SPL=1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1". ・ Input enabled Indicates that the input function can be used. ・ Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L". ・ Hi-Z Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state. ・ Setting disabled Indicates that the setting is disabled. ・ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ・ Analog input is enabled Indicates that the analog input is enabled. ・ Trace output Indicates that the trace function can be used. DS706-00010-1v0-E 57
Page 1 and 2:
FUJITSU SEMICONDUCTOR DATA SHEET Co
Page 3 and 4:
MB9B500 Series Multi-function Seri
Page 5 and 6: Dual Timer (Two 32/16bit Down Count
Page 7 and 8: PRODUCT LINEUP MB9B500 Series Memo
Page 9 and 10: PIN ASSIGNMENT FPT-100P-M20/M23 VS
Page 11 and 12: BGA-112P-M04 MB9B500 Series ・ Th
Page 13 and 14: Pin no. LQFP-100 BGA-112 LQFP-120 D
Page 25 and 26: MB9B500 Series SIGNAL DESCRIPTION
Page 27 and 28: MB9B500 Series The number after the
Page 41 and 42: MB9B500 Series Type Circuit Remarks
Page 43 and 44: MB9B500 Series Type Circuit Remarks
Page 45 and 46: MB9B500 Series PRECAUTIONS FOR HAN
Page 47 and 48: MB9B500 Series Precautions for Pac
Page 49 and 50: HANDLING DEVICES MB9B500 Series Po
Page 51 and 52: HANDLING MB9BF500 MB9B500 Series H
Page 53 and 54: MB9BF504/505/506 Block Diagram TRST
Page 55: MB9B500 Series Memory Map(2) 0x2008
Page 59 and 60: Pin status type Power-on reset or l
Page 61 and 62: Pin status type Function group Powe
Page 63 and 64: MB9B500 Series 2. Absolute Maximum
Page 65 and 66: DC Characteristics The following ta
Page 67 and 68: MB9B500 Series (2) MB9BF504/505/506
Page 69 and 70: MB9B500 Series 2. Pin Characteristi
Page 71 and 72: MB9B500 Series (2) Sub Clock Input
Page 73 and 74: MB9B500 Series (7) External Bus Tim
Page 75 and 76: MB9B500 Series ・ NAND FLASH mode
Page 77 and 78: (8) Base Timer Input Timing ・ Tim
Page 79 and 80: SCK SOT SIN SCK SOT SIN V IH tF DS7
Page 81 and 82: S C K S O T S IN S C K S O T S IN V
Page 83 and 84: SCK SOT SIN SCK SOT SIN *2 VOH VO L
Page 85 and 86: SCK SOT SIN SCK SOT SIN VOH VOL MB9
Page 87 and 88: MB9B500 Series (11) Quadrature Posi
Page 89 and 90: MB9B500 Series (12) I 2 C timing (V
Page 91 and 92: MB9B500 Series (14) JTAG timing (Vc
Page 93 and 94: (Continued) MB9B500 Series The outp
Page 95 and 96: MB9B500 Series ・ Setting examples
Page 97 and 98: MB9B500 Series ・ Setting examples
Page 99 and 100: ・Definition of 10-bit A/D Convert
Page 101 and 102: 12bit A/D Converter This chapter sh
Page 103 and 104: ・Definition of 12-bit A/D Convert
Page 105 and 106: MB9B500 Series *3 : The output driv
Page 107 and 108:
(Continued) Figure 1 Low-Speed Load
Page 109 and 110:
Flash Memory Write/Erase Characteri
Page 111 and 112:
Power supply current (Sub timer mod
Page 113 and 114:
PACKAGE DIMENSIONS 100-pin plastic
Page 115 and 116:
(Continued) 120-pin plastic LQFP (F
Page 117 and 118:
MAJOR CHANGES IN THIS EDITION Page
Page 119 and 120:
DS706-00010-1v0-E MB9B500 Series 11
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FM3 MB9B500 Series - Microcontrollers - Fujitsu

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