FM3 MB9B500 Series - Microcontrollers - Fujitsu

MB9B500 Series
(12) I 2 C timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40C to + 85C)
Typical High-speed
Parameter Symbol Conditions mode mode Unit Remarks
Min Max Min Max
SCL clock frequency
(Repeated) START condition
fSCL 0 100 0 400 kHz
hold time
SDA SCL
tHDSTA 4.0 - 0.6 - μs
SCLclock "L" width tLOW 4.7 - 1.3 - μs
SCLclock "H" width tHIGH 4.0 - 0.6 - μs
(Repeated) START setup time
SCL SDA
tSUSTA
CL = 50pF,
4.7 - 0.6 - μs
Data hold time
SCL SDA
tHDDAT
R = (Vp/IOL)
(*1)
0
3.45
(*2)
0
0.9
(*3)
μs
Data setup time
SDA SCL
tSUDAT 250 - 100 - ns
STOP condition setup time
SCL SDA
Bus free time between
tSUSTO 4.0 - 0.6 - μs
"STOP condition" and
"START condition"
tBUF
4.7 - 1.3 - μs
2 tCYCP
2 tCYCP
Noise filter tSP -
-
- ns
(*4) (*4)
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL
signal.
*3 : A high-speed mode I 2 C bus device can be used on a standard mode I 2 C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the peripheral clock cycle time. To use I 2 C, set the peripheral bus clock at 8 MHz or more.
SDA
SCL
tHDSTA
tLOW
DS706-00010-1v0-E
tHDDAT
tSUDAT
tHIGH
tSUSTA
tHDSTA tSP
tSUSTO
tBUF
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