VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
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Two-Level versus Multilevel<br />
2-Level:<br />
f 1 = AB + AC + AD<br />
f 2 = AB + AC + AE<br />
6 product terms which cannot be shared.<br />
24 transistors in static CMOS<br />
Multi-level:<br />
Note that B + C is a common term in f 1 <strong>and</strong> f 2<br />
K = B + C 3 Levels<br />
f1 =ΑΚ+AD<br />
f2 = AK + AE<br />
20 transistors in static CMOS<br />
not counting inverters<br />
4
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