VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
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Tech.-Independent Optimization<br />
Involves:<br />
Minimizing two-level logic functions.<br />
Finding common subexpressions.<br />
Substituting one expression into another.<br />
Factoring single functions.<br />
Factored versus Disjunctive forms<br />
f = ac + ad + bc + bd + ae<br />
sum-of-products or disjunctive form<br />
f = ( a + b ) ( c + d ) + ae<br />
factored form<br />
multi-level or complex gate<br />
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