VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...
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Final <strong>Placement</strong> - 1<br />
Earlier steps have broken down the problem into a manageable<br />
number of objects<br />
Two approaches:<br />
Kurt Keutzer<br />
Final placement for st<strong>and</strong>ard cells/gate array – row<br />
assignment<br />
Final placement for large, irregularly sized macro-blocks –<br />
slicing – won’t talk about this<br />
25
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