VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...

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Basic Rules of Routing – Part 3 Routing can be on a fixed or gridless (aka area routing) Case 1: Detailed routing over cells Wiring can go over cells Design of cells must try to minimize obstacles to routing – I.e. minimize use of metal-1, metal-2 Cells do not need to bring signals (i.e. inputs, outputs) out to the channel – the route will come to them ECE 260B – CSE 241A /UCB EECS 244 8 Kahng/Keutzer/Newton
Graph Search Steiner Iterative ECE 260B – CSE 241A /UCB EECS 244 9 Taxonomy of VLSI Routers River Switchbox Channel Routers Global Detailed Specialized Restricted General Purpose Hierarchical Greedy Left-Edge Courtesy K. Keutzer et al. UCB Maze Line Probe Line Expansion Power & Ground Clock Kahng/Keutzer/Newton
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VLSI CAD Flow: Logic Synthesis, Pla
Page 3 and 4:
Two-Level Logic Minimization Can re
Page 5 and 6:
Technologies “Closed book”: gat
Page 7 and 8:
Optimizations F = ⎧ ⎨ ⎩ Facto
Page 9 and 10:
Algebraic vs. Boolean Methods Algeb
Page 11 and 12:
Strong (or Boolean) Division Given
Page 13 and 14:
Weak (or Algebraic) Division Defini
Page 15 and 16: Weak Division Example f = abc + abd
Page 17 and 18: Tech.-Dependent Optimization LIBRAR
Page 19 and 20: Mapping via DAG Covering Represent
Page 21 and 22: Sample Library - 2 AOI21 4 AOI22 5
Page 23 and 24: Covering #1 2 INV = 4 2 NAND2 = 6 1
Page 25 and 26: DAG Covering Sound Algorithmic appr
Page 27 and 28: Resulting Trees Break at multiple f
Page 29 and 30: Optimum Tree Covering INV 2 NAND2 3
Page 31 and 32: Physical Design: Overall Conceptual
Page 33 and 34: Results of Placement Kurt Keutzer B
Page 35 and 36: Gordian: A Quadratic Placement Appr
Page 37 and 38: Improving the intuitive formulation
Page 39 and 40: Toy Example: Kurt Keutzer Cost =(x
Page 41 and 42: Global Optimization Using Quadratic
Page 43 and 44: Layout After Global Optimization A.
Page 45 and 46: Partitioning Kurt Keutzer In GORDIA
Page 47 and 48: Adding Positioning Constraints •
Page 49 and 50: First Iteration Kurt Keutzer A. Kah
Page 51 and 52: Third Iteration Kurt Keutzer A. Kah
Page 53 and 54: Final Placement
Page 55 and 56: Final Placement - Standard Cell Des
Page 57 and 58: Kurt Keutzer Standard Cell Layout 2
Page 59 and 60: Physical Design Flow Input Floorpla
Page 61 and 62: What are some of your consideration
Page 63 and 64: Routing Algorithms Hard to tackle h
Page 65: Basic Rules of Routing - Part 2 Ro
Page 69 and 70: Top-down problems in the flow initi
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VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 ...

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