AN-8027 — FAN480X PFC+PWM Combination Controller Application

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AN-8027 60dB 40dB 20dB 0dB -20dB -40dB Control-to-output Compensation Closed Loop Gain 10Hz 100Hz 1kHz 10kHz 100kHz Figure 17. Current Loop Compensation f IZ f IC f IP 1MHz (Design Example) Setting the crossover frequency as 7 kHz: vCS1 RCS1VBOUT v V 2fL IEA @ f f RAMP IC BOOST IC 0.1387 0.66 3 6 2.55 2 7 10 524 10 1 1 RIC 17k 6 v 88100.66 CS1 GMI v IEA @ f fIC 1 1 C 4nF 2 / 3 17 10 2 7 10 / 3 IC1 3 3 RICfC Setting the pole of the compensator at 70kHz, 1 1 C 0.13nF IC2 3 3 2 fIPRIC270101710 [STEP-9] PFC Voltage Loop Design Since FAN480X employs line feed-forward, the power stage transfer function becomes independent of the line voltage. Then, the low-frequency, small-signal, control-tooutput transfer function is obtained as: vˆ BOUT vˆ EA IBOUT KMAX 1 5 sCBOUT (37) where: vˆ BOUT vˆ IBOUT KMAX 1 5 sC (38) EA BOUT Proportional and integration (PI) control with highfrequency pole is typically used for compensation. The compensation zero (fVZ) introduces phase boost, while the high-frequency compensation pole (fVP) attenuates the switching ripple, as shown in Figure 18. © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.2 • 6/21/13 10 60dB 40dB 20dB 0dB -20dB -40dB Closed-Loop Gain Control-to-Output fc Compensation 1Hz 10Hz 100Hz 1kHz Figure 18. Voltage Loop Compensation 10kHz The transfer function of the compensation network is obtained as: s 1 vˆ 2 f 2 f vˆ s OUT s 1 2 f COMP VI VZ where: 2.5 fVI V GMV 2 C , 1 fVZ 2 R C and f VP VP BOUT VC1 VC VC1 1 2 R C VC VC 2 The procedure to design the feedback loop is as follows: (39) (40) (a) Determine the crossover frequency (fVC) around 1/10~1/5 of the line frequency. Since the control-tooutput transfer function of power stage has -20 dB/dec slope and -90 o phase at the crossover frequency, as shown in Figure 18 as 0dB; it is necessary to place the zero of the compensation network (fVZ) around the crossover frequency so that 45 phase margin is obtained. Then, the capacitor CVC1 is determined as: GMV IBOUTKMAX2.5 CVC1 2 (41) 5 CBOUT(2 fVC) VBOUT To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: R VC 1 2 f C VC VC1 (42) (b) Place compensator high-frequency pole (fVP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter so noise can be effectively attenuated. Then, the capacitor CVC2 is determined as: C VC2 1 2 f R VP VC (43)
AN-8027 (Design Example) Setting the crossover frequency as 22 Hz: C G IK 2.5 V MV BOUT MAX VC1 2 5 CBOUT(2 fVC) BOUT 6 7010 0.91.27 2.5 6 2 20nF 5 270 10 (2 22) 387 1 1 RVC 362k 9 2 f C 2 22 20 10 VC VC1 Setting the pole of the compensator at 120 Hz: 1 1 C 3.7nF VC2 3 2 fVPRVC212036210 [STEP-10] Transformer Design for PWM Stage Figure 19 shows the typical secondary-side circuit of forward converter for multi-output of PC power application. A common technique for winding multiple outputs with the same polarity sharing a common ground is to stack the secondary windings instead of winding each output winding separately. This approach improves the load regulation of the stacked outputs. The winding NS1 in Figure 19 must be sized to accommodate its output current, plus the current of the output (+12 V) stacked on top of it. To get tight regulation of 3.3 V output, magnetic amplifier (MAG-AMP) is used. The saturable core of MAG-AMP prevents the diode DREC from fully conducting by introducing high impedance until it is saturated. This allows the effective duty cycle of VREC to be controlled to be regulated the output voltage. N p N S 1 MAG AMP N S 2 D REC N S 3 V REC + - MAG AMP Control Additiona l LC filter Additiona l LC filter Additiona l LC filter Additiona l LC filter Figure 19. Typical Secondary-Side Circuit +12V +5V +3.3 V -12V Once the core for the transformer is determined, the minimum number of turns for the transformer primary-side to avoid saturation is given by: V D MIN MIN BOUT MAX NP (44) Ae fSW B where Ae is the cross sectional area of the core in m 2 , fSW is the switching frequency, and B is the maximum flux density swing in Tesla for normal operation. B is typically 0.2-0.3 T for most power ferrite cores in the case of a forward converter. The turn ratio between the primary-side and secondaryside winding for the first output is determined by: MIN NP VBOUTDMAX n (45) NS1 ( VO1 VF 1) where VF is the diode forward-voltage drop. Next, determine the proper integer for NS1 resulting in Np larger than Np min . Once the number of turns of the first output is determined, the number of turns of other output (n-th output) can be determined by: V V N N O( n) F ( n) S ( n) S1 VO1VF1 © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.2 • 6/21/13 11 (46) The golden ratio between the secondary-side windings for the best regulation of 3.3 V, 5 V, and 12 V is known as 2:3:7. (Design Example) The minimum PFC output voltage is 310 V and the maximum duty cycle of PWM controller is 50%. By adding 5% margin to the maximum duty cycle, DMAX=0.45 is used for transformer design. Assuming ERL35 (Ae=107 mm 2 ) core is used and B=0.28, the minimum turns for the transformer primary side is obtained as: N MIN V D 310 0.45 72 6 3 A f B 10710 65 10 0.28 MIN BOUT MAX P e SW The turns ratio for 5 V output is obtained as: MIN NP VBOUTDMAX3100.45 n 25.6 N ( V V) (5 0.45) S O F The number of turns for the primary-side winding is determined as: N n N 1 2 25.6 51.2 N MIN p S P N n N 3 25.6 76.8 N N 3 MIN p S1 P S1 Then, the turns ratio for 12-V output is obtained as: V V 12 0.7 N N 3 6.99 7 5 0.45 O2 F2 S2 VO1 VF1 S1 Therefore, the number of turns for each winding is obtained as: Np=78, NS1=3, NS2=7 (3+4 stack) and NS3=7.
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AN-8027 — FAN480X PFC+PWM Combination Controller Application

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