AN-8027 — FAN480X PFC+PWM Combination Controller Application

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AN-8027 I D, AVG I D I D, AVG I BOUT (1 cos(4 fLINE t)) VBOUT V BOUT , RIPPLE IBOUT 2 f C Figure 14. PFC Output Voltage Ripple I BOUT LINE BOUT (Design Example) With the ripple specification of 12 VPP, the capacitor should be: IBOUT 0.9 CBOUT239F 2 f V 25012 LINE BOUT , RIPPLE Since minimum allowable output voltage during one cycle line (20 ms) drop-outs is 310 V, the capacitor should be: PBOUTtHOLD 3 2 349 2010 2 OUT 2 OUT , MIN 2 2 387 310 CBOUT260F V V Thus, 270 F capacitor is selected for the PFC output capacitor. [STEP-6] PFC Output Sensing Circuit To improve system efficiency at low line and light load condition, FAN480X provides two-level PFC output voltage. As shown in Figure 15, FAN480X monitors VEA and VRMS voltages to adjust the PFC output voltage. The PFC output voltage when 20 µA is enabled is given as: 20μAR V V - 2.5 FB2 BOUT 2 BOUT (1 ) (25) It is typical second boost output voltage as 340 V~300 V. © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.2 • 6/21/13 8 RFB1 RFB2 VBOUT FBPFC 2.5V VDD 20uA - + 1.95/2.45 + - 1.95/2.45 For FAN4801S, VEA threshold is 2.8/3.35V. Figure 15. Two-Level PFC Output Block VRMS VEA The voltage divider network for the PFC output voltage sensing should be designed such that FBPFC voltage is 2.5V at nominal PFC output voltage: R FB2 VBOUT 2.5V RFB1RFB2 (Design Example) Assuming the second level of PFC output voltage is 347 V: R V 2.5 (1 ) 20 10 BOUT 2 FB2 VBOUT 6 347 2.5 (1 ) 12.9k 6 387 2010 13 k is selected for RFB2. R V ( 2.5 387 2.5 1) R BOUT FB1 FB2 3 ( 1) 1310 1999k 2 M is selected for RFB1. (26) [STEP-7] PFC Current-Sensing Circuit Design Figure 16 shows the PFC compensation circuits. The first step in compensation network design is to select the currentsensing resistor of PFC converter considering the control window of voltage loop. Since line feed-forward is used in FAN480X, the output power is proportional to the voltage control error amplifier voltage as: V P ( V ) P V MAX EA BOUT EA BOUT SAT EA 0.6 0.6 (27) where VEA SAT is 5.6 V and the maximum power limit of PFC is: V GR (28) 2 MAX MAX LINE. BO M BOUT RIACRCS1 P
AN-8027 It is typical to set the maximum power limit of PFC stage around 1.2~1.5 of its nominal power such that the VEA is around 4~4.5 V at nominal output power. By adjusting the current-sensing resistor for PFC stage, the maximum power limit of PFC stage can be programmed. To filter out the current ripple of switching frequency, an RC filter is typically used for ISENSE pin. RLF1 should not be larger than 100 Ω and the cut-off frequency of filter should be 1/2~1/6 of the switching frequency. Diodes D1 and D2 are required to prevent over-voltage on the ISENSE pin due to the inrush current that might damage the IC. A fast recovery diode or ultra fast recovery diode is recommended. CRMS1 CRMS2 RRMS1 VIN RRMS2 RRMS3 RVC2 RIAC IAC RF1 ISENS E CF1 IA C VRMS VEA RV C RVC1 IL RCS1 RM R M IM O + - 2.5V Drive logic Figure 16. Gain Modulation Block VO IEA RI C CIC2 CIC1 VREF OPFC FBPFC (Design Example) Setting the maximum power limit of PFC stage as 450W, the current sensing resistor is obtained as: R 2 MAX 2 3 LINE. BO M CS1 MAX RIACPBOUT 6 610450 RFB1 RFB2 V GR7295.710 0.098 Thus, 0.1- resistor is selected. [STEP-8] PFC Current Loop Design The transfer function from duty cycle to the inductor current of boost power stage is given as: iL V d sL BOUT BOOST (29) The transfer function from the output of the current control error amplifier to the inductor current-sensing voltage is obtained as: v R V v V sL 1 1 CS CS BOUT IEA RAMP BOOST (30) where VRAMP is the peak to peak voltage of ramp signal for current control PWM comparator, which is 2.55 V. The transfer function of the compensation circuit is given as: s 1 vIEA2fII2f v s CS1 s 1 2 f where: G 1 f , f and II MI 2 CIC1 IZ 2 RIC CIC1 1 2 R C IC IC 2 © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.2 • 6/21/13 9 f IP IC IP The procedure to design the feedback loop is as follows: (31) (32) (a) Determine the crossover frequency (fIC) around 1/10~1/6 of the switching frequency. Then calculate the gain of the transfer function of Equation (30) at crossover frequency as: vCS1 RCS1VBOUT v V 2fL IEA @ f f RAMP IC BOOST IC (33) (b) Calculate RIC that makes the closed loop gain unity at crossover frequency: R IC G MI v 1 CS1 vIEA @ f fIC (34) (c) Since the control-to-output transfer function of power stage has -20 dB/dec slope and -90 o phase at the crossover frequency is 0 dB, as shown in Figure 17; it is necessary to place the zero of the compensation network (fIZ) around 1/3 of the crossover frequency so that more than 45 phase margin is obtained. Then the capacitor CIC1 is determined as: C IC1 1 R 2 f / 3 IC C (35) (d) Place compensator high-frequency pole (fCP) at least a decade higher than fIC to ensure that it does not interfere with the phase margin of the current loop at its crossover frequency. C IC 2 1 2 f R IP IC (36)
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AN-8027 — FAN480X PFC+PWM Combination Controller Application

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