Robust System Design - VLSI
Robust System Design - VLSI
Robust System Design - VLSI
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IFRA Hardware in Superscalar Processor<br />
FETCH<br />
DECODE<br />
DISPATCH<br />
ISSUE<br />
EXECUTE<br />
COMMIT<br />
Branch Predictor I-TLB I-Cache<br />
Fetch Queue ID assignment<br />
Pipeline Registers<br />
Decoders<br />
Pipeline Registers<br />
Reg Map Reg Free<br />
Pipeline Registers<br />
Instruction Window<br />
Pipeline Registers<br />
MUL 2xALU<br />
2xBr FPU 2xLSU<br />
Pipeline Registers<br />
Reg Rename<br />
Phys Regfile<br />
D-Cache<br />
D-TLB<br />
Reorder Buffer Reg Map<br />
Pipeline Registers<br />
Recorders<br />
Recorders<br />
Recorders<br />
Recorders<br />
Recorders<br />
Recorders<br />
Alpha 21264<br />
(open source)<br />
Part of<br />
scan chain<br />
No at-speed<br />
routing<br />
Post-Trigger<br />
Generator<br />
12
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