Robust System Design - VLSI
Robust System Design - VLSI
Robust System Design - VLSI
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What to Record ?<br />
Pipeline<br />
stage<br />
Auxiliary information<br />
Description Bits per recorder<br />
Number of<br />
recorders<br />
Fetch Program Counter 32 4<br />
Decode Decoding results 4 4<br />
Dispatch Register names residue 6 4<br />
Issue Operands residue 6 4<br />
Execution<br />
(ALU, MUL)<br />
Result residue 3 4<br />
Execution None 0 2<br />
(Branch)<br />
Execution<br />
(Load/Store)<br />
Result residue;<br />
Memory address<br />
35 2<br />
Total required storage for all recorders: 60 KBytes<br />
15
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