Robust System Design - VLSI

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Special Rule for Instruction ID Simplistic schemes inadequate Speculation + flushes, out-of-order, loops Multiple clocks, voltage frequency scaling Special rule [Park TCAD 09] ID width: log 24n bits n = max. instructions in flight 8 bits for Alpha (n = 64) No timestamp or global synchronization 14
What to Record ? Pipeline stage Auxiliary information Description Bits per recorder Number of recorders Fetch Program Counter 32 4 Decode Decoding results 4 4 Dispatch Register names residue 6 4 Issue Operands residue 6 4 Execution (ALU, MUL) Result residue 3 4 Execution None 0 2 (Branch) Execution (Load/Store) Result residue; Memory address 35 2 Total required storage for all recorders: 60 KBytes 15
Page 1 and 2: Robust System Design Subhasish Mitr
Page 3 and 4: Who Cares About Soft Errors ? 20K
Page 5 and 6: Robust System Design Challenges Rad
Page 7 and 8: Outline Introduction Thorough val
Page 9 and 10: Post-Silicon Bug Localization Chall
Page 11 and 12: IFRA Principle Design Phase Post-Si
Page 13: Recording Example FETCH DECODE Bran
Page 17 and 18: Post-Analysis Overview Test program
Page 19 and 20: Debug Example Link footprints HLA1
Page 21 and 22: Outline Introduction Thorough val
Page 23 and 24: Low-cost Resilience Failure rate Bu
Page 25 and 26: Architecture-Aware BISER Insertion
Page 27 and 28: Single Event Multiple Upsets (SEMU)
Page 29 and 30: Circuit Failure Prediction Early I
Page 31 and 32: Standard Normal Quantile Ids [µA]
Page 33 and 34: On-line Self-Test & Diagnostics: CA
Page 35 and 36: CASP for SUN OpenSPARC T1 Cores Te
Page 37 and 38: Hardware-Only CASP Inefficient I/O
Page 39 and 40: CASP for Uncore in SoCs ? Uncore C
Page 41 and 42: Carbon Nanotube (CNT) FETs: Big Pro
Page 43: Conclusion Robust system design E

Robust System Design - VLSI

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