Robust System Design - VLSI
Robust System Design - VLSI
Robust System Design - VLSI
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Who Cares About Soft Errors ?<br />
20K processors server farm<br />
1 major flip-flop error every 20 days<br />
Silent data corruption<br />
$ 20K $ 3,616 bank deposit<br />
Downtime: $100K - $10M / hr.<br />
Memory ECC routinely used<br />
<strong>System</strong> error rates increasing<br />
Comb. logic<br />
Flipflop<br />
Un<br />
protected<br />
memory<br />
Soft error rate<br />
contributions<br />
3
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