Robust System Design - VLSI
Robust System Design - VLSI
Robust System Design - VLSI
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CASP for Uncore in SoCs ?<br />
Uncore CASP challenging<br />
Multiple uncore copies not available<br />
Multiple cores affected during uncore CASP<br />
Uncore significant : OpenSPARC T2 (8-cores, 64 threads)<br />
Memory BIST +<br />
Self-repair<br />
Memory<br />
Cores<br />
Core CASP<br />
Uncore<br />
New Uncore CASP<br />
Utilize self-similarity<br />
[VTS 10]<br />
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