Robust System Design - VLSI

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Circuit Failure Prediction Applicability Degradation delay SHIFT ≠ delay fault Transistor aging e.g., Negative Bias Temperature Instability Adaptive (≠ worst-case) guardbands Gate-oxide Early-Life Failures (ELF) Burn-in alternatives 30
Standard Normal Quantile Ids [µA] after 5340 min stress New Gate-oxide ELF Signature: 90nm Delay shifts over time: distinct from NBTI, PBTI, hot-e 4 2 0 -2 -4 -6 90 80 70 60 50 40 30 240 min. stress 5340 min. stress 20 40 60 80 100 Ids[µA] W = 0.2µm Fresh Outliers 20 60 70 80 90 100 Fresh Ids [µA] 10 min. stress 952 pairs: I ds outliers 11.6% of entire population Outliers Y 60 50 40 30 20 10 885 pairs 92% Outlier locations random in 0.2µm array 0 0 50 100 150 200 250 X 952 pairs: Largest I g increase 11.6% of entire population Delay Shifts [ps] 1,500 1,000 500 0 Iddq [A] at VDD=1V 10-4 10-4 10-4 10-5 10-5 10-5 10-6 10-6 10-6 10-7 10-7 10-7 Inverter chain input LOW Inverter chain input HIGH 0 20 40 60 80 100 Rising transition Stress Time [sec] 100X Delay jump -500 0 20 40 60 80 100 Stress Time [sec] Falling transition 31
Page 1 and 2: Robust System Design Subhasish Mitr
Page 3 and 4: Who Cares About Soft Errors ? 20K
Page 5 and 6: Robust System Design Challenges Rad
Page 7 and 8: Outline Introduction Thorough val
Page 9 and 10: Post-Silicon Bug Localization Chall
Page 11 and 12: IFRA Principle Design Phase Post-Si
Page 13 and 14: Recording Example FETCH DECODE Bran
Page 15 and 16: What to Record ? Pipeline stage Aux
Page 17 and 18: Post-Analysis Overview Test program
Page 19 and 20: Debug Example Link footprints HLA1
Page 21 and 22: Outline Introduction Thorough val
Page 23 and 24: Low-cost Resilience Failure rate Bu
Page 25 and 26: Architecture-Aware BISER Insertion
Page 27 and 28: Single Event Multiple Upsets (SEMU)
Page 29: Circuit Failure Prediction Early I
Page 33 and 34: On-line Self-Test & Diagnostics: CA
Page 35 and 36: CASP for SUN OpenSPARC T1 Cores Te
Page 37 and 38: Hardware-Only CASP Inefficient I/O
Page 39 and 40: CASP for Uncore in SoCs ? Uncore C
Page 41 and 42: Carbon Nanotube (CNT) FETs: Big Pro
Page 43: Conclusion Robust system design E

Robust System Design - VLSI

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