Robust System Design - VLSI
Robust System Design - VLSI
Robust System Design - VLSI
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Architecture-Aware BISER Insertion<br />
cumulative error coverage<br />
100%<br />
80%<br />
60%<br />
40%<br />
20%<br />
10X chip-level protection<br />
2X<br />
2.5%<br />
power<br />
penalty<br />
0%<br />
0% 20% 40% 60% 80% 100%<br />
cumulative latch coverage<br />
Alpha 21264<br />
error injection<br />
9% chip-level<br />
power penalty<br />
Ack: Prof. S.J. Patel,<br />
UIUC for error injector<br />
Optimized BISER insertion: verification-guided ?<br />
25
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