Robust System Design - VLSI
Robust System Design - VLSI
Robust System Design - VLSI
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Reconfigurable Correction – Economy Mode<br />
Scan Clock<br />
B = 1<br />
Scan Data<br />
Scan Clock A<br />
Capture = 0<br />
Update<br />
<strong>System</strong><br />
Data<br />
<strong>System</strong><br />
Clock<br />
1D<br />
C1<br />
Scan / Checking Flip-flop<br />
1D<br />
C1<br />
2D<br />
C2<br />
Q<br />
1D<br />
Q Q<br />
C1<br />
Integrated design quality<br />
+<br />
&<br />
1D<br />
C1<br />
2D<br />
C2<br />
Q<br />
<strong>System</strong> Flip- flop<br />
Scan<br />
Output<br />
C-element Keeper<br />
<strong>System</strong><br />
Output<br />
Soft error correction, scan test, post-silicon debug 26
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