H8SX/1665MZ Group Hardware Manual - Renesas Electronics

9.6.2 I/O Pins Used for Basic Bus Interface .............................................................. 238
9.6.3 Basic Timing..................................................................................................... 239
9.6.4 Wait Control ..................................................................................................... 245
9.6.5 Read Strobe (RD) Timing................................................................................. 247
9.6.6 Extension of Chip Select (CS) Assertion Period............................................... 248
9.6.7 DACK and EDACK Signal Output Timing...................................................... 250
9.7 Byte Control SRAM Interface .......................................................................................... 251
9.7.1 Byte Control SRAM Space Setting................................................................... 251
9.7.2 Data Bus ........................................................................................................... 251
9.7.3 I/O Pins Used for Byte Control SRAM Interface ............................................. 252
9.7.4 Basic Timing..................................................................................................... 253
9.7.5 Wait Control ..................................................................................................... 255
9.7.6 Read Strobe (RD) ............................................................................................. 257
9.7.7 Extension of Chip Select (CS) Assertion Period............................................... 257
9.7.8 DACK and EDACK Signal Output Timing...................................................... 257
9.8 Burst ROM Interface ........................................................................................................ 259
9.8.1 Burst ROM Space Setting................................................................................. 259
9.8.2 Data Bus ........................................................................................................... 259
9.8.3 I/O Pins Used for Burst ROM Interface............................................................ 260
9.8.4 Basic Timing..................................................................................................... 261
9.8.5 Wait Control ..................................................................................................... 263
9.8.6 Read Strobe (RD) Timing................................................................................. 263
9.8.7 Extension of Chip Select (CS) Assertion Period............................................... 263
9.9 Address/Data Multiplexed I/O Interface........................................................................... 264
9.9.1 Address/Data Multiplexed I/O Space Setting ................................................... 264
9.9.2 Address/Data Multiplex.................................................................................... 264
9.9.3 Data Bus ........................................................................................................... 264
9.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 265
9.9.5 Basic Timing..................................................................................................... 266
9.9.6 Address Cycle Control...................................................................................... 268
9.9.7 Wait Control ..................................................................................................... 269
9.9.8 Read Strobe (RD) Timing................................................................................. 269
9.9.9 Extension of Chip Select (CS) Assertion Period............................................... 271
9.9.10 DACK and EDACK Signal Output Timing...................................................... 273
9.10 DRAM Interface ............................................................................................................... 274
9.10.1 Setting DRAM Space........................................................................................ 274
9.10.2 Address Multiplexing ....................................................................................... 274
9.10.3 Data Bus ........................................................................................................... 275
9.10.4 I/O Pins Used for DRAM Interface .................................................................. 275
9.10.5 Basic Timing..................................................................................................... 276
Rev. 1.00 Jan. 29, 2010 Page xiv of xxxii