H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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Section 1 Overview 1.2 List of Products Table 1.3 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.3 List of Products Group Part No. ROM Capacity RAM Capacity Package Remarks H8SX/1665MZ R5F61665MZN50FPV 512 Kbytes 40 Kbytes LQFP-144 Regular specifications Rev. 1.00 Jan. 29, 2010 Page 10 of 1402 REJ09B0597-0100
Section 1 Overview Part No. R 5 F 61665MZN50 FP V Indicates the Pb-free version. Indicates the package. FP: LQFP Indicates the product-specific number. N: Regular specifications • Small Package Indicates the type of ROM device. F: On-chip flash memory Product classification Microcontroller Indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Name Code Package Package Code Body Size Pin Pitch LQFP-144 PLQP0144KA-A (FP-144LV)* 20.0 × 20.0 mm 0.50 mm Note: * Pb-free version Rev. 1.00 Jan. 29, 2010 Page 11 of 1402 REJ09B0597-0100
Page 1 and 2: REJ09B0597-0100 H8SX/1665MZ Group 3
Page 3 and 4: Notes regarding these materials 1.
Page 5 and 6: How to Use This Manual 1. Objective
Page 7 and 8: 3. Description of Registers Each re
Page 9 and 10: Contents Section 1 Overview........
Page 11 and 12: 4.2 Input/Output Pin ..............
Page 13 and 14: 8.3.2 Break Address Mask Register n
Page 15 and 16: 9.10.6 Controlling Column Address O
Page 17 and 18: 11.3.2 EXDMA Destination Address Re
Page 19 and 20: Section 13 I/O Ports...............
Page 21 and 22: 14.10.11 Conflict between Overflow/
Page 23 and 24: Section 18 Watchdog Timer (WDT)....
Page 25 and 26: Section 20 USB Function Module (USB
Page 27 and 28: 21.4.6 Noise Canceler..............
Page 29 and 30: 25.11 Switching between User MAT an
Page 31 and 32: 28.12.2 Current Consumption during
Page 33 and 34: Section 1 Overview Section 1 Overvi
Page 35 and 36: Section 1 Overview Classification C
Page 37 and 38: Section 1 Overview Classification E
Page 39 and 40: Section 1 Overview Classification T
Page 41: Section 1 Overview Table 1.2 Compar
Page 45 and 46: Section 1 Overview 1.4 Pin Assignme
Page 47 and 48: Section 1 Overview Pin No. Pin Name
Page 53 and 54: Section 1 Overview Classification P
Page 61 and 62: Section 2 CPU Section 2 CPU The H8S
Page 63 and 64: Section 2 CPU 2.2 CPU Operating Mod
Page 65 and 66: Section 2 CPU 2.2.2 Middle Mode The
Page 67 and 68: Section 2 CPU • Stack Structure T
Page 69 and 70: Section 2 CPU 2.3 Instruction Fetch
Page 71 and 72: Section 2 CPU 2.5.1 General Registe
Page 73 and 74: Section 2 CPU 2.5.3 Condition-Code
Page 75 and 76: Section 2 CPU 2.5.5 Vector Base Reg
Page 77 and 78: Section 2 CPU 2.6.2 Memory Data For
Page 79 and 80: Section 2 CPU Function Instructions
Page 81 and 82: Section 2 CPU Classification Instru
Page 83 and 84: Section 2 CPU Table 2.2 Combination
Page 85 and 86: Section 2 CPU Table 2.4 Data Transf
Page 87 and 88: Section 2 CPU Table 2.6 Arithmetic
Page 89 and 90: Section 2 CPU Table 2.7 Logic Opera
Page 91 and 92: Section 2 CPU Instruction Size Func
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Section 2 CPU Table 2.11 System Con
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Section 2 CPU 2.8 Addressing Modes
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Section 2 CPU 2.8.5 Register Indire
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Section 2 CPU 2.8.7 Immediate—#xx
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Section 2 CPU 2.8.11 Extended Memor
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Section 2 CPU Table 2.15 Effective
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Section 2 CPU Request for exception
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Section 3 MCU Operating Modes Secti
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Section 3 MCU Operating Modes 3.2 R
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Section 3 MCU Operating Modes 3.2.2
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Section 3 MCU Operating Modes 3.3 O
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Section 3 MCU Operating Modes 3.3.8
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Section 3 MCU Operating Modes H'000
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Section 4 Resets Section 4 Resets 4
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Section 4 Resets Note that some reg
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Section 4 Resets Bit Bit Name Initi
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Section 4 Resets 4.4 Pin Reset This
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Section 4 Resets 4.7 Deep Software
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Section 5 Voltage Detection Circuit
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Section 6 Exception Handling Sectio
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Section 6 Exception Handling Vector
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Section 6 Exception Handling 6.3.2
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Section 6 Exception Handling 6.4 Tr
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Section 6 Exception Handling Bus Cy
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Section 6 Exception Handling 6.6 In
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Section 6 Exception Handling 6.7 In
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Section 6 Exception Handling 6.7.3
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Section 6 Exception Handling 6.9 Us
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Section 7 Interrupt Controller Sect
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Section 7 Interrupt Controller 7.2
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Section 7 Interrupt Controller 7.3.
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Section 7 Interrupt Controller Bit
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Tabl
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Section 7 Interrupt Controller (2)
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Section 7 Interrupt Controller The
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Section 8 User Break Controller (UB
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Section 9 Bus Controller (BSC) Sect
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Section 9 Bus Controller (BSC) A bl
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Section 9 Bus Controller (BSC) 9.2.
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Section 9 Bus Controller (BSC) Bit
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Section 9 Bus Controller (BSC) Bus
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Section 9 Bus Controller (BSC) 9.4
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Section 9 Bus Controller (BSC) Divi
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Section 9 Bus Controller (BSC) Name
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Section 9 Bus Controller (BSC) Area
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Section 9 Bus Controller (BSC) (4)
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Section 9 Bus Controller (BSC) Numb
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Section 9 Bus Controller (BSC) Stro
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Section 9 Bus Controller (BSC) Addr
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Section 9 Bus Controller (BSC) To e
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Section 9 Bus Controller (BSC) Wait
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Section 9 Bus Controller (BSC) T p
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Section 9 Bus Controller (BSC) (b)
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Section 9 Bus Controller (BSC) Pφ
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Section 9 Bus Controller (BSC) This
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Section 9 Bus Controller (BSC) SDRA
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Section 9 Bus Controller (BSC) The
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Section 9 Bus Controller (BSC) (b)
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Section 9 Bus Controller (BSC) A re
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Section 9 Bus Controller (BSC) Bφ
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Section 9 Bus Controller (BSC) •
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Section 9 Bus Controller (BSC) Exte
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Section 10 DMA Controller (DMAC) Se
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Section 10 DMA Controller (DMAC) A
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Section 10 DMA Controller (DMAC) 10
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Bi
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Section 10 DMA Controller (DMAC) In
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Ad
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Section 10 DMA Controller (DMAC) Tr
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Section 10 DMA Controller (DMAC) (2
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Section 10 DMA Controller (DMAC) Fi
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Section 10 DMA Controller (DMAC) Th
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Section 10 DMA Controller (DMAC) Wh
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Section 10 DMA Controller (DMAC) In
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Section 10 DMA Controller (DMAC) DM
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Section 10 DMA Controller (DMAC) TS
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Section 11 EXDMA Controller (EXDMAC
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Section 12 Data Transfer Controller
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Section 13 I/O Ports Section 13 I/O
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Section 13 I/O Ports Function Port
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Section 13 I/O Ports 13.1 Register
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Section 13 I/O Ports 13.1.2 Data Re
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Section 13 I/O Ports 13.1.5 Pull-Up
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Section 13 I/O Ports 13.2 Output Bu
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Section 13 I/O Ports (4) P14/DREQ1-
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Section 13 I/O Ports (8) P10/DREQ0-
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Section 13 I/O Ports (4) P24/PO4/TI
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Section 13 I/O Ports (4) P34/PO12/T
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Section 13 I/O Ports (3) P63/TMRI3/
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Section 13 I/O Ports 13.2.6 Port A
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Section 13 I/O Ports (5) PA3/LLWR/L
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Section 13 I/O Ports 13.2.7 Port B
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Section 13 I/O Ports (5) PB3/CS3/CS
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Section 13 I/O Ports 13.2.8 Port C
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Section 13 I/O Ports (1) PE7/A15, P
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Section 13 I/O Ports (4) PF4/A20 Th
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Section 13 I/O Ports (8) PF0/A16 Th
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Section 13 I/O Ports 13.2.14 Port J
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Section 13 I/O Ports (5) PJ3 The pi
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Section 13 I/O Ports 13.2.15 Port K
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Section 13 I/O Ports (5) PK3 The pi
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Section 13 I/O Ports 13.2.16 Port M
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Section 13 I/O Ports Table 13.5 Ava
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Section 13 I/O Ports Port P2 0 P3 7
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Section 13 I/O Ports Port Output Sp
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Section 13 I/O Ports Port PB PC PD
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Section 13 I/O Ports Port PI PM Out
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Section 13 I/O Ports Bit Bit Name I
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Section 13 I/O Ports 13.3.6 Port Fu
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Section 13 I/O Ports 13.3.10 Port F
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Section 13 I/O Ports 13.4 Usage Not
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Section 14 16-Bit Timer Pulse Unit
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Section 15 Programmable Pulse Gener
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Section 16 8-Bit Timers (TMR) Secti
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Section 16 8-Bit Timers (TMR) Inter
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Section 16 8-Bit Timers (TMR) Clock
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Section 16 8-Bit Timers (TMR) 16.3
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Section 16 8-Bit Timers (TMR) 16.3.
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Section 16 8-Bit Timers (TMR) Bit B
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Pφ E
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Section 17 32K Timer (TM32K) Sectio
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Section 17 32K Timer (TM32K) Bit Bi
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Section 17 32K Timer (TM32K) 17.3 O
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Section 17 32K Timer (TM32K) To ave
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Section 17 32K Timer (TM32K) 17.5 U
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Section 18 Watchdog Timer (WDT) Sec
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Section 18 Watchdog Timer (WDT) 18.
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Section 18 Watchdog Timer (WDT) H'F
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Section 19 Serial Communication Int
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Section 20 USB Function Module (USB
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Section 21 I 2 C Bus Interface 2 (I
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Section 22 A/D Converter Section 22
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Section 22 A/D Converter Module dat
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Section 22 A/D Converter 22.3 Regis
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Section 22 A/D Converter 22.3.2 A/D
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Section 22 A/D Converter Bit 3 2 1
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Section 22 A/D Converter Bit Bit Na
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Section 22 A/D Converter Set* ADIE
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Section 22 A/D Converter A/D conver
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Section 22 A/D Converter 22.4.3 Inp
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Section 22 A/D Converter Table 22.3
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Section 22 A/D Converter Pφ ADTRG0
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Section 22 A/D Converter 22.6 A/D C
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Section 22 A/D Converter 22.7 Usage
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Section 22 A/D Converter Start Exte
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Section 22 A/D Converter 22.7.6 Inf
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Section 23 D/A Converter Section 23
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Section 23 D/A Converter 23.3.1 D/A
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Section 23 D/A Converter 23.3.5 D/A
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Section 23 D/A Converter 23.4 Opera
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Section 23 D/A Converter 23.5 Usage
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Section 24 RAM Section 24 RAM This
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Section 25 Flash Memory Section 25
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Section 25 Flash Memory 25.2 Mode T
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Section 25 Flash Memory 25.3 Memory
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Section 25 Flash Memory 25.5 Progra
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Section 25 Flash Memory 25.6 Input/
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Section 25 Flash Memory Table 25.3
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Section 25 Flash Memory Bit Bit Nam
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Section 25 Flash Memory (2) Flash P
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Section 25 Flash Memory (5) Flash M
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Section 25 Flash Memory 25.7.2 Prog
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Section 25 Flash Memory (2) Downloa
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Section 25 Flash Memory (b) Program
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Section 25 Flash Memory (c) Erasure
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Section 25 Flash Memory Bit Bit Nam
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Section 25 Flash Memory (6) Flash M
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Section 25 Flash Memory 25.7.3 RAM
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Section 25 Flash Memory 25.8.1 Boot
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Section 25 Flash Memory (2) State T
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Section 25 Flash Memory 25.8.2 USB
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Section 25 Flash Memory (2) State T
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Section 25 Flash Memory 25.8.3 User
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Section 25 Flash Memory (2) Program
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Section 25 Flash Memory ⎯ The ret
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Section 25 Flash Memory ⎯ Example
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Section 25 Flash Memory The procedu
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Section 25 Flash Memory In figure 2
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Section 25 Flash Memory In user boo
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Section 25 Flash Memory Memory MAT
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Section 25 Flash Memory 25.9 Protec
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Section 25 Flash Memory Error prote
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Section 25 Flash Memory Figure 25.2
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Section 25 Flash Memory 25.11 Switc
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Section 25 Flash Memory 3. Programm
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Section 25 Flash Memory (f) Operati
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Section 25 Flash Memory • Area-la
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Section 25 Flash Memory Error Respo
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Section 25 Flash Memory (5) Transit
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Section 25 Flash Memory (8) Program
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Section 25 Flash Memory • Erasure
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Section 25 Flash Memory (c) 128-Byt
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Section 25 Flash Memory (e) Block E
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Section 25 Flash Memory (g) User Bo
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Section 25 Flash Memory (k) Boot Pr
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Section 25 Flash Memory 25.14 Usage
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Section 26 Boundary Scan Section 26
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Section 26 Boundary Scan 26.4 Regis
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Section 26 Boundary Scan Table 26.3
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Section 26 Boundary Scan Pin No Pin
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Section 26 Boundary Scan Pin No Pin
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Section 26 Boundary Scan 26.4.4 IDC
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Section 26 Boundary Scan 26.5.2 Com
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Section 26 Boundary Scan 26.6 Usage
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Section 27 Clock Pulse Generator Se
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Section 27 Clock Pulse Generator 27
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Section 27 Clock Pulse Generator Bi
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Section 27 Clock Pulse Generator Fi
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Section 28 Power-Down Modes Section
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Section 28 Power-Down Modes Notes:
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Section 28 Power-Down Modes 28.2 Re
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Section 28 Power-Down Modes Bit Bit
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Section 28 Power-Down Modes • MST
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Section 28 Power-Down Modes • MST
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Section 28 Power-Down Modes Bit 7 6
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Section 28 Power-Down Modes 28.2.6
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Section 28 Power-Down Modes 28.3 Mu
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Section 28 Power-Down Modes 28.5 Sl
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Section 28 Power-Down Modes 28.7 So
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Section 28 Power-Down Modes 28.8 De
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Section 28 Power-Down Modes 4. Exit
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Section 28 Power-Down Modes Oscilla
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Section 28 Power-Down Modes (3) Dee
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Section 28 Power-Down Modes Clear a
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Section 28 Power-Down Modes SLPIE =
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Section 28 Power-Down Modes 28.12 U
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Section 28 Power-Down Modes Rev. 1.
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Section 29 List of Registers 29.1 R
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Section 29 List of Registers Access
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Section 29 List of Registers 29.2 R
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Section 29 List of Registers Regist
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Section 29 List of Registers Notes:
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Section 29 List of Registers Rev. 1
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Section 30 Electrical Characteristi
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t WDD t WDS2 t WDH3 Section 30 Elec
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Appendix Port Name PA2/ BREQ/ WAIT
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Appendix Port Name PB6/ CS6-D/ (RD/
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Appendix B. Product Lineup Product
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Appendix D. Treatment of Unused Pin
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Appendix Rev. 1.00 Jan. 29, 2010 Pa
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Cluster transfer modes.............
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P Package dimensions...............
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PODRH .............................
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Rev. 1.00 Jan. 29, 2010 Page 1402 o
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Sales Strategic Planning Div. Nippo
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H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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