H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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28.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) ........ 1220 28.2.3 Module Stop Control Register C (MSTPCRC)............................................... 1224 28.2.4 Deep Standby Control Register (DPSBYCR)................................................. 1225 28.2.5 Deep Standby Wait Control Register (DPSWCR).......................................... 1227 28.2.6 Deep Standby Interrupt Enable Register (DPSIER) ....................................... 1229 28.2.7 Deep Standby Interrupt Flag Register (DPSIFR)............................................ 1231 28.2.8 Deep Standby Interrupt Edge Register (DPSIEGR) ....................................... 1233 28.2.9 Reset Status Register (RSTSR)....................................................................... 1234 28.2.10 Deep Standby Backup Register (DPSBKRn) ................................................. 1236 28.3 Multi-Clock Function ..................................................................................................... 1237 28.3.1 Switching of Main Clock Frequencies............................................................ 1237 28.3.2 Switching to Subclock .................................................................................... 1237 28.4 Module Stop State........................................................................................................... 1238 28.5 Sleep Mode..................................................................................................................... 1239 28.5.1 Entry to Sleep Mode ....................................................................................... 1239 28.5.2 Exit from Sleep Mode..................................................................................... 1239 28.6 All-Module-Clock-Stop Mode........................................................................................ 1240 28.7 Software Standby Mode.................................................................................................. 1241 28.7.1 Entry to Software Standby Mode.................................................................... 1241 28.7.2 Exit from Software Standby Mode ................................................................. 1241 28.7.3 Setting Oscillation Settling Time after Exit from Software Standby Mode.... 1243 28.7.4 Software Standby Mode Application Example............................................... 1244 28.8 Deep Software Standby Mode ........................................................................................ 1245 28.8.1 Entry to Deep Software Standby Mode .......................................................... 1245 28.8.2 Exit from Deep Software Standby Mode........................................................ 1246 28.8.3 Pin State on Exit from Deep Software Standby Mode.................................... 1247 28.8.4 Bφ/SDRAMφ Operation after Exit from Deep Software Standby Mode........ 1248 28.8.5 Setting Oscillation Settling Time after Exit from Deep Software Standby Mode................................................................ 1249 28.8.6 Deep Software Standby Mode Application Example ..................................... 1250 28.8.7 Flowchart of Deep Software Standby Mode Operation.................................. 1254 28.9 Hardware Standby Mode ................................................................................................ 1256 28.9.1 Transition to Hardware Standby Mode........................................................... 1256 28.9.2 Clearing Hardware Standby Mode.................................................................. 1256 28.9.3 Hardware Standby Mode Timing.................................................................... 1256 28.9.4 Timing Sequence at Power-On ....................................................................... 1257 28.10 Sleep Instruction Exception Handling ............................................................................ 1258 28.11 φ Clock Output Control .................................................................................................. 1261 28.12 Usage Notes.................................................................................................................... 1262 28.12.1 I/O Port Status................................................................................................. 1262 Rev. 1.00 Jan. 29, 2010 Page xxx of xxxii
28.12.2 Current Consumption during Oscillation Settling Standby Period ................. 1262 28.12.3 Module Stop State of EXDMAC, DMAC, or DTC ........................................ 1262 28.12.4 On-Chip Peripheral Module Interrupts ........................................................... 1262 28.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC..................................... 1262 28.12.6 Control of Input Buffers by DIRQnE (n = 3 to 0)........................................... 1263 28.12.7 Conflict between a transition to deep standby mode and interrupts................ 1263 28.12.8 Bφ/SDRAMφ Output State ............................................................................. 1263 Section 29 List of Registers .............................................................................1265 29.1 Register Addresses (Address Order)............................................................................... 1266 29.2 Register Bits.................................................................................................................... 1282 29.3 Register States in Each Operating Mode ........................................................................ 1309 Section 30 Electrical Characteristics ...............................................................1327 30.1 Absolute Maximum Ratings ........................................................................................... 1327 30.2 DC Characteristics .......................................................................................................... 1328 30.3 AC Characteristics .......................................................................................................... 1331 30.3.1 Clock Timing .................................................................................................. 1331 30.3.2 Control Signal Timing .................................................................................... 1334 30.3.3 Bus Timing ..................................................................................................... 1335 30.3.4 DMAC and EXDMAC Timing....................................................................... 1366 30.3.5 Timing of On-Chip Peripheral Modules ......................................................... 1370 30.4 USB Characteristics........................................................................................................ 1377 30.5 A/D Conversion Characteristics ..................................................................................... 1379 30.6 D/A Conversion Characteristics ..................................................................................... 1381 30.7 Flash Memory Characteristics ........................................................................................ 1382 30.8 Power-On Reset Circuit and Voltage-Detection Circuit Characteristics ........................ 1383 Appendix............................................................................................................1385 A. Port States in Each Pin State........................................................................................... 1385 B. Product Lineup................................................................................................................ 1390 C. Package Dimensions....................................................................................................... 1391 D. Treatment of Unused Pins............................................................................................... 1392 Index ..................................................................................................................1395 Rev. 1.00 Jan. 29, 2010 Page xxxi of xxxii
Page 1 and 2: REJ09B0597-0100 H8SX/1665MZ Group 3
Page 3 and 4: Notes regarding these materials 1.
Page 5 and 6: How to Use This Manual 1. Objective
Page 7 and 8: 3. Description of Registers Each re
Page 9 and 10: Contents Section 1 Overview........
Page 11 and 12: 4.2 Input/Output Pin ..............
Page 13 and 14: 8.3.2 Break Address Mask Register n
Page 15 and 16: 9.10.6 Controlling Column Address O
Page 17 and 18: 11.3.2 EXDMA Destination Address Re
Page 19 and 20: Section 13 I/O Ports...............
Page 21 and 22: 14.10.11 Conflict between Overflow/
Page 23 and 24: Section 18 Watchdog Timer (WDT)....
Page 25 and 26: Section 20 USB Function Module (USB
Page 27 and 28: 21.4.6 Noise Canceler..............
Page 29: 25.11 Switching between User MAT an
Page 33 and 34: Section 1 Overview Section 1 Overvi
Page 35 and 36: Section 1 Overview Classification C
Page 37 and 38: Section 1 Overview Classification E
Page 39 and 40: Section 1 Overview Classification T
Page 41 and 42: Section 1 Overview Table 1.2 Compar
Page 43 and 44: Section 1 Overview Part No. R 5 F 6
Page 45 and 46: Section 1 Overview 1.4 Pin Assignme
Page 47 and 48: Section 1 Overview Pin No. Pin Name
Page 53 and 54: Section 1 Overview Classification P
Page 61 and 62: Section 2 CPU Section 2 CPU The H8S
Page 63 and 64: Section 2 CPU 2.2 CPU Operating Mod
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Page 67 and 68: Section 2 CPU • Stack Structure T
Page 69 and 70: Section 2 CPU 2.3 Instruction Fetch
Page 71 and 72: Section 2 CPU 2.5.1 General Registe
Page 73 and 74: Section 2 CPU 2.5.3 Condition-Code
Page 75 and 76: Section 2 CPU 2.5.5 Vector Base Reg
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Page 79 and 80: Section 2 CPU Function Instructions
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Section 2 CPU Classification Instru
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Section 2 CPU Table 2.2 Combination
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Section 2 CPU Table 2.4 Data Transf
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Section 2 CPU Table 2.6 Arithmetic
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Section 2 CPU Table 2.7 Logic Opera
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Section 2 CPU Instruction Size Func
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Section 2 CPU Table 2.11 System Con
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Section 2 CPU 2.8 Addressing Modes
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Section 2 CPU 2.8.5 Register Indire
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Section 2 CPU 2.8.7 Immediate—#xx
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Section 2 CPU 2.8.11 Extended Memor
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Section 2 CPU Table 2.15 Effective
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Section 2 CPU Request for exception
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Section 3 MCU Operating Modes Secti
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Section 3 MCU Operating Modes 3.2 R
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Section 3 MCU Operating Modes 3.2.2
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Section 3 MCU Operating Modes 3.3 O
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Section 3 MCU Operating Modes 3.3.8
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Section 3 MCU Operating Modes H'000
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Section 4 Resets Section 4 Resets 4
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Section 4 Resets Note that some reg
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Section 4 Resets Bit Bit Name Initi
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Section 4 Resets 4.4 Pin Reset This
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Section 4 Resets 4.7 Deep Software
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Section 5 Voltage Detection Circuit
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Section 6 Exception Handling Sectio
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Section 6 Exception Handling Vector
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Section 6 Exception Handling 6.3.2
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Section 6 Exception Handling 6.4 Tr
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Section 6 Exception Handling Bus Cy
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Section 6 Exception Handling 6.6 In
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Section 6 Exception Handling 6.7 In
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Section 6 Exception Handling 6.7.3
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Section 6 Exception Handling 6.9 Us
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Section 7 Interrupt Controller Sect
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Section 7 Interrupt Controller 7.2
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Section 7 Interrupt Controller 7.3.
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Section 7 Interrupt Controller Bit
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Tabl
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Section 7 Interrupt Controller (2)
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Section 7 Interrupt Controller The
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Section 8 User Break Controller (UB
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Section 9 Bus Controller (BSC) Sect
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Section 9 Bus Controller (BSC) A bl
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Section 9 Bus Controller (BSC) 9.2.
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Section 9 Bus Controller (BSC) Bit
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Section 9 Bus Controller (BSC) Bus
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Section 9 Bus Controller (BSC) 9.4
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Section 9 Bus Controller (BSC) Divi
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Section 9 Bus Controller (BSC) Name
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Section 9 Bus Controller (BSC) Area
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Section 9 Bus Controller (BSC) (4)
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Section 9 Bus Controller (BSC) Numb
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Section 9 Bus Controller (BSC) Addr
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Section 9 Bus Controller (BSC) To e
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Section 9 Bus Controller (BSC) Wait
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Section 9 Bus Controller (BSC) (b)
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Section 9 Bus Controller (BSC) Bφ
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Section 10 DMA Controller (DMAC) Se
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Section 10 DMA Controller (DMAC) A
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Section 10 DMA Controller (DMAC) 10
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Bi
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Section 10 DMA Controller (DMAC) In
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Ad
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Section 10 DMA Controller (DMAC) (2
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Section 10 DMA Controller (DMAC) Th
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Section 10 DMA Controller (DMAC) DM
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Section 10 DMA Controller (DMAC) TS
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Section 11 EXDMA Controller (EXDMAC
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Section 12 Data Transfer Controller
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Section 13 I/O Ports Section 13 I/O
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Section 13 I/O Ports Function Port
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Section 13 I/O Ports 13.1 Register
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Section 13 I/O Ports 13.1.2 Data Re
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Section 13 I/O Ports 13.1.5 Pull-Up
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Section 13 I/O Ports 13.2 Output Bu
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Section 13 I/O Ports (4) P14/DREQ1-
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Section 13 I/O Ports (8) P10/DREQ0-
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Section 13 I/O Ports (4) P24/PO4/TI
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Section 13 I/O Ports (4) P34/PO12/T
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Section 13 I/O Ports (3) P63/TMRI3/
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Section 13 I/O Ports 13.2.6 Port A
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Section 13 I/O Ports (5) PA3/LLWR/L
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Section 13 I/O Ports 13.2.7 Port B
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Section 13 I/O Ports (5) PB3/CS3/CS
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Section 13 I/O Ports 13.2.8 Port C
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Section 13 I/O Ports (1) PE7/A15, P
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Section 13 I/O Ports (4) PF4/A20 Th
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Section 13 I/O Ports (8) PF0/A16 Th
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Section 13 I/O Ports 13.2.14 Port J
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Section 13 I/O Ports (5) PJ3 The pi
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Section 13 I/O Ports 13.2.15 Port K
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Section 13 I/O Ports (5) PK3 The pi
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Section 13 I/O Ports 13.2.16 Port M
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Section 13 I/O Ports Table 13.5 Ava
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Section 13 I/O Ports Port P2 0 P3 7
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Section 13 I/O Ports Port Output Sp
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Section 13 I/O Ports Port PB PC PD
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Section 13 I/O Ports Port PI PM Out
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Section 13 I/O Ports Bit Bit Name I
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Section 13 I/O Ports 13.3.6 Port Fu
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Section 13 I/O Ports 13.3.10 Port F
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Section 13 I/O Ports 13.4 Usage Not
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Section 14 16-Bit Timer Pulse Unit
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Section 15 Programmable Pulse Gener
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Section 16 8-Bit Timers (TMR) Secti
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Section 16 8-Bit Timers (TMR) Inter
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Section 16 8-Bit Timers (TMR) Clock
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Section 16 8-Bit Timers (TMR) 16.3
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Section 16 8-Bit Timers (TMR) 16.3.
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Section 16 8-Bit Timers (TMR) Bit B
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Pφ E
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Section 17 32K Timer (TM32K) Sectio
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Section 17 32K Timer (TM32K) Bit Bi
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Section 17 32K Timer (TM32K) 17.3 O
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Section 17 32K Timer (TM32K) To ave
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Section 17 32K Timer (TM32K) 17.5 U
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Section 18 Watchdog Timer (WDT) Sec
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Section 18 Watchdog Timer (WDT) 18.
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Section 18 Watchdog Timer (WDT) H'F
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Section 19 Serial Communication Int
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Section 22 A/D Converter Section 22
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Section 22 A/D Converter Set* ADIE
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Section 22 A/D Converter Table 22.3
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Section 22 A/D Converter Pφ ADTRG0
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Section 22 A/D Converter 22.6 A/D C
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Section 22 A/D Converter 22.7 Usage
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Section 23 D/A Converter Section 23
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Section 23 D/A Converter 23.3.5 D/A
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Section 23 D/A Converter 23.4 Opera
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Section 23 D/A Converter 23.5 Usage
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Section 24 RAM Section 24 RAM This
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Section 25 Flash Memory Section 25
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Section 25 Flash Memory 25.2 Mode T
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Section 25 Flash Memory 25.3 Memory
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Section 25 Flash Memory 25.5 Progra
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Section 25 Flash Memory 25.6 Input/
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Section 25 Flash Memory Table 25.3
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Section 25 Flash Memory (2) Flash P
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Section 25 Flash Memory (5) Flash M
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Section 25 Flash Memory 25.7.2 Prog
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Section 25 Flash Memory (2) Downloa
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Section 25 Flash Memory (b) Program
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Section 25 Flash Memory (c) Erasure
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Section 25 Flash Memory Bit Bit Nam
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Section 25 Flash Memory (6) Flash M
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Section 25 Flash Memory 25.7.3 RAM
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Section 25 Flash Memory 25.8.1 Boot
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Section 25 Flash Memory (2) State T
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Section 25 Flash Memory 25.8.2 USB
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Section 25 Flash Memory (2) State T
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Section 25 Flash Memory 25.8.3 User
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Section 25 Flash Memory (2) Program
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Section 25 Flash Memory ⎯ The ret
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Section 25 Flash Memory ⎯ Example
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Section 25 Flash Memory The procedu
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Section 25 Flash Memory In figure 2
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Section 25 Flash Memory In user boo
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Section 25 Flash Memory Memory MAT
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Section 25 Flash Memory 25.9 Protec
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Section 25 Flash Memory Error prote
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Section 25 Flash Memory Figure 25.2
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Section 25 Flash Memory 25.11 Switc
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Section 25 Flash Memory 3. Programm
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Section 25 Flash Memory 5. Memory r
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Section 25 Flash Memory The selecti
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Section 25 Flash Memory (d) Clock M
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Section 25 Flash Memory (f) Operati
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Section 25 Flash Memory • Area-la
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Section 25 Flash Memory Error Respo
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Section 25 Flash Memory (5) Transit
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Section 25 Flash Memory (8) Program
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Section 25 Flash Memory • Erasure
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Section 25 Flash Memory (c) 128-Byt
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Section 25 Flash Memory (e) Block E
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Section 25 Flash Memory (g) User Bo
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Section 25 Flash Memory (k) Boot Pr
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Section 25 Flash Memory 25.14 Usage
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Section 26 Boundary Scan Section 26
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Section 26 Boundary Scan 26.4 Regis
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Section 26 Boundary Scan Table 26.3
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Section 26 Boundary Scan Pin No Pin
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Section 26 Boundary Scan Pin No Pin
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Section 26 Boundary Scan 26.4.4 IDC
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Section 26 Boundary Scan 26.5.2 Com
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Section 26 Boundary Scan 26.6 Usage
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Section 27 Clock Pulse Generator Se
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Section 27 Clock Pulse Generator 27
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Section 27 Clock Pulse Generator Bi
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Section 27 Clock Pulse Generator Fi
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Section 28 Power-Down Modes Section
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Section 28 Power-Down Modes Notes:
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Section 28 Power-Down Modes 28.2 Re
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Section 28 Power-Down Modes Bit Bit
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Section 28 Power-Down Modes • MST
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Section 28 Power-Down Modes • MST
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Section 28 Power-Down Modes Bit 7 6
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Section 28 Power-Down Modes 28.2.6
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Section 28 Power-Down Modes 28.3 Mu
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Section 28 Power-Down Modes 28.5 Sl
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Section 28 Power-Down Modes 28.7 So
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Section 28 Power-Down Modes 28.8 De
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Section 28 Power-Down Modes 4. Exit
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Section 28 Power-Down Modes Oscilla
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Section 28 Power-Down Modes (3) Dee
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Section 28 Power-Down Modes Clear a
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Section 28 Power-Down Modes SLPIE =
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Section 28 Power-Down Modes 28.12 U
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Section 28 Power-Down Modes Rev. 1.
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Section 29 List of Registers 29.1 R
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Section 29 List of Registers Access
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Section 29 List of Registers 29.2 R
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Section 29 List of Registers Regist
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Section 29 List of Registers Notes:
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Section 29 List of Registers Rev. 1
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Section 30 Electrical Characteristi
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t WDD t WDS2 t WDH3 Section 30 Elec
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Appendix Port Name PA2/ BREQ/ WAIT
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Appendix Port Name PB6/ CS6-D/ (RD/
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Appendix B. Product Lineup Product
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Appendix D. Treatment of Unused Pin
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Appendix Rev. 1.00 Jan. 29, 2010 Pa
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Cluster transfer modes.............
Page 1430 and 1431:
P Package dimensions...............
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PODRH .............................
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Rev. 1.00 Jan. 29, 2010 Page 1402 o
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Sales Strategic Planning Div. Nippo
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H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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