H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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Rev. 1.00 Jan. 29, 2010 Page xxxii of xxxii
Section 1 Overview Section 1 Overview 1.1 Features The core of products in the H8SX/1665MZ Group of CISC (complex instruction set computer) microcontrollers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcontrollers; H8/300, H8/300H, and H8S. As peripheral functions, each LSI of the Group includes a DMA controller and an EXDMA controller which enable high-speed data transfer, and a bus-state controller, which enables direct connection to different kinds of memory. The LSI of the Group also includes serial communications interfaces, A/D and D/A converters, and a multi-function timer that makes motor control easy. Together, the modules realize low-cost configurations for end systems. The power consumption of these modules is kept down dynamically by an on-chip power-management function. The on-chip ROM is a flash memory (F-ZTAT TM *) with a capacity of 512 Kbytes (H8SX/1665MZ). Note: * F-ZTAT TM is a trademark of Renesas Technology Corp. 1.1.1 Applications Examples of the applications of this LSI include PC peripheral equipment, optical storage devices, office automation equipment, and industrial equipment. Rev. 1.00 Jan. 29, 2010 Page 1 of 1402 REJ09B0597-0100
Page 1 and 2: REJ09B0597-0100 H8SX/1665MZ Group 3
Page 3 and 4: Notes regarding these materials 1.
Page 5 and 6: How to Use This Manual 1. Objective
Page 7 and 8: 3. Description of Registers Each re
Page 9 and 10: Contents Section 1 Overview........
Page 11 and 12: 4.2 Input/Output Pin ..............
Page 13 and 14: 8.3.2 Break Address Mask Register n
Page 15 and 16: 9.10.6 Controlling Column Address O
Page 17 and 18: 11.3.2 EXDMA Destination Address Re
Page 19 and 20: Section 13 I/O Ports...............
Page 21 and 22: 14.10.11 Conflict between Overflow/
Page 23 and 24: Section 18 Watchdog Timer (WDT)....
Page 25 and 26: Section 20 USB Function Module (USB
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Page 29 and 30: 25.11 Switching between User MAT an
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Page 47 and 48: Section 1 Overview Pin No. Pin Name
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Page 61 and 62: Section 2 CPU Section 2 CPU The H8S
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Section 2 CPU Table 2.2 Combination
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Section 2 CPU Table 2.4 Data Transf
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Section 2 CPU Table 2.6 Arithmetic
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Section 2 CPU Instruction Size Func
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Section 2 CPU Table 2.11 System Con
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Section 2 CPU 2.8 Addressing Modes
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Section 2 CPU 2.8.5 Register Indire
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Section 2 CPU 2.8.7 Immediate—#xx
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Section 2 CPU 2.8.11 Extended Memor
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Section 2 CPU Table 2.15 Effective
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Section 2 CPU Request for exception
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Section 3 MCU Operating Modes Secti
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Section 3 MCU Operating Modes 3.2 R
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Section 3 MCU Operating Modes 3.2.2
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Section 3 MCU Operating Modes 3.3 O
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Section 3 MCU Operating Modes 3.3.8
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Section 3 MCU Operating Modes H'000
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Section 4 Resets Section 4 Resets 4
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Section 4 Resets Note that some reg
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Section 4 Resets Bit Bit Name Initi
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Section 4 Resets 4.7 Deep Software
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Section 5 Voltage Detection Circuit
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Section 6 Exception Handling Sectio
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Section 6 Exception Handling Vector
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Section 6 Exception Handling 6.3.2
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Section 6 Exception Handling 6.4 Tr
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Section 6 Exception Handling Bus Cy
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Section 6 Exception Handling 6.6 In
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Section 6 Exception Handling 6.7 In
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Section 6 Exception Handling 6.7.3
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Section 6 Exception Handling 6.9 Us
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Section 7 Interrupt Controller Sect
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Section 7 Interrupt Controller 7.2
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Section 7 Interrupt Controller Bit
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Tabl
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Section 7 Interrupt Controller (2)
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Section 8 User Break Controller (UB
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Section 9 Bus Controller (BSC) Sect
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Section 9 Bus Controller (BSC) 9.2.
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Section 9 Bus Controller (BSC) Bit
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Section 9 Bus Controller (BSC) 9.4
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Section 9 Bus Controller (BSC) Name
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Section 9 Bus Controller (BSC) Area
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Section 9 Bus Controller (BSC) Numb
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Section 9 Bus Controller (BSC) Bφ
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Section 9 Bus Controller (BSC) •
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Section 10 DMA Controller (DMAC) Se
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Section 10 DMA Controller (DMAC) A
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Bi
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Section 10 DMA Controller (DMAC) In
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Section 10 DMA Controller (DMAC) (2
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Section 10 DMA Controller (DMAC) Th
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Section 10 DMA Controller (DMAC) Wh
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Section 10 DMA Controller (DMAC) In
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Section 10 DMA Controller (DMAC) DM
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Section 10 DMA Controller (DMAC) TS
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Section 11 EXDMA Controller (EXDMAC
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Section 12 Data Transfer Controller
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Section 13 I/O Ports Section 13 I/O
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Section 13 I/O Ports 13.1 Register
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Section 13 I/O Ports 13.1.2 Data Re
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Section 13 I/O Ports 13.1.5 Pull-Up
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Section 13 I/O Ports (4) P14/DREQ1-
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Section 13 I/O Ports 13.2.6 Port A
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Section 13 I/O Ports (5) PA3/LLWR/L
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Section 13 I/O Ports 13.2.7 Port B
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Section 13 I/O Ports (5) PB3/CS3/CS
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Section 13 I/O Ports 13.2.8 Port C
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Section 13 I/O Ports (1) PE7/A15, P
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Section 13 I/O Ports (4) PF4/A20 Th
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Section 13 I/O Ports 13.2.14 Port J
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Section 13 I/O Ports (5) PJ3 The pi
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Section 13 I/O Ports 13.2.15 Port K
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Section 13 I/O Ports (5) PK3 The pi
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Section 13 I/O Ports 13.2.16 Port M
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Section 13 I/O Ports Table 13.5 Ava
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Section 13 I/O Ports Port Output Sp
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Section 13 I/O Ports Port PB PC PD
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Section 13 I/O Ports 13.4 Usage Not
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Section 14 16-Bit Timer Pulse Unit
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Section 15 Programmable Pulse Gener
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Section 16 8-Bit Timers (TMR) Secti
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Section 16 8-Bit Timers (TMR) 16.3
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Pφ E
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Section 17 32K Timer (TM32K) Sectio
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Section 17 32K Timer (TM32K) 17.3 O
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Section 17 32K Timer (TM32K) 17.5 U
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Section 18 Watchdog Timer (WDT) Sec
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Section 18 Watchdog Timer (WDT) 18.
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Section 18 Watchdog Timer (WDT) H'F
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Section 19 Serial Communication Int
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Section 23 D/A Converter 23.5 Usage
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Section 24 RAM Section 24 RAM This
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Section 25 Flash Memory Section 25
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Section 26 Boundary Scan Section 26
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Section 26 Boundary Scan 26.5.2 Com
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Section 26 Boundary Scan 26.6 Usage
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Section 27 Clock Pulse Generator Se
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Section 27 Clock Pulse Generator 27
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Section 27 Clock Pulse Generator Bi
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Section 27 Clock Pulse Generator Fi
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Section 28 Power-Down Modes Section
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Section 28 Power-Down Modes Notes:
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Section 28 Power-Down Modes 28.2 Re
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Section 28 Power-Down Modes Bit Bit
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Section 28 Power-Down Modes • MST
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Section 28 Power-Down Modes • MST
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Section 28 Power-Down Modes Bit 7 6
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Section 28 Power-Down Modes 28.2.6
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Section 28 Power-Down Modes 28.3 Mu
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Section 28 Power-Down Modes 28.5 Sl
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Section 28 Power-Down Modes 28.7 So
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Section 28 Power-Down Modes 28.8 De
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Section 28 Power-Down Modes 4. Exit
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Section 28 Power-Down Modes Oscilla
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Section 28 Power-Down Modes (3) Dee
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Section 28 Power-Down Modes Clear a
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Section 28 Power-Down Modes SLPIE =
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Section 28 Power-Down Modes 28.12 U
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Section 28 Power-Down Modes Rev. 1.
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Section 29 List of Registers 29.1 R
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Section 29 List of Registers Access
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Section 29 List of Registers 29.2 R
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Section 29 List of Registers Regist
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Section 29 List of Registers Notes:
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Section 29 List of Registers Rev. 1
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Section 30 Electrical Characteristi
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t WDD t WDS2 t WDH3 Section 30 Elec
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Appendix Port Name PA2/ BREQ/ WAIT
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Appendix Port Name PB6/ CS6-D/ (RD/
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Appendix B. Product Lineup Product
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Appendix D. Treatment of Unused Pin
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Appendix Rev. 1.00 Jan. 29, 2010 Pa
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Cluster transfer modes.............
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P Package dimensions...............
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PODRH .............................
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Rev. 1.00 Jan. 29, 2010 Page 1402 o
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Sales Strategic Planning Div. Nippo
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H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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