H8SX/1665MZ Group Hardware Manual - Renesas Electronics

Section 1 Overview
1.3 Block Diagram
TM32K
Port 1
WDT
Port 2
RAM
ROM
H8SX
CPU
Internal system bus
Interrupt
controller
BSC
Internal peripheral bus
TMR × 2 channels
(unit 0)
TMR × 2 channels
(unit 1)
TMR × 2 channels
(unit 2)
TMR × 2 channels
(unit 3)
TPU × 6 channels
PPG × 16 channels
Port 3
Port 5
Port 6
Port A
Port B
DTC
DMAC ×
4 channels
SCI × 4 channels
USB
Port C
Port D/
port J*
Main clock
oscillator
EXDMAC ×
2 channels
IIC2 × 2 channels
10-bit AD × 4
channels (unit 0)
Port E/
port K*
Port F
Subclock
oscillator
POR/LVD
Internal system bus
External bus
10-bit AD × 4
channels (unit 1)
10-bit DA ×
2 channels
Port H
Port I
Port M
[Legend]
CPU: Central processing unit
DTC: Data transfer controller
BSC: Bus controller
DMAC: DMA controller
EXDMAC: EXDMA controller
TM32K: 32K timer
WDT: Watchdog timer
Note:
TMR:
TPU:
PPG:
SCI:
USB:
IIC2:
POR/LVD:
8-bit timer
16-bit timer pulse unit
Programmable pulse generator
Serial communications interface
Universal serial bus interface
IIC bus interface 2
Power-on reset / Low voltage detection circuit
* In single-chip mode, the port D and port E functions can be used in the initial state.
Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled
when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external
extended mode, only ports D and E can be used.
Figure 1.2 Block Diagram
Rev. 1.00 Jan. 29, 2010 Page 12 of 1402
REJ09B0597-0100