H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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Section 1 Overview Pin No. Pin Name LQFP- 144 Modes 1, 2, and 6 Modes 3 and 7 Modes 4 and 5 102 STBY STBY STBY 103 Vss Vss Vss 104 P35/PO13/TIOCA1/TIOCB1/ TCLKC-A/DACK1-B P35/PO13/TIOCA1/TIOCB1/ TCLKC-A/DACK1-B P35/PO13/TIOCA1/TIOCB1/ TCLKC-A/DACK1-B 105 P36/PO14/TIOCA2 P36/PO14/TIOCA2 P36/PO14/TIOCA2 106 P37/PO15/TIOCA2/TIOCB2/ TCLKD-A 107 P60/TMRI2/TxD4/DREQ2/ IRQ8-B/EDREQ0-B 108 P61/TMCI2/RxD4/TEND2/ IRQ9-B/ETEND0-B 109 P62/TMO2/SCK4/DACK2/ IRQ10-B/EDACK0-B P37/PO15/TIOCA2/TIOCB2/ TCLKD-A P60/TMRI2/TxD4/DREQ2/ IRQ8-B/EDREQ0-B P61/TMCI2/RxD4/TEND2/ IRQ9-B/ETEND0-B P62/TMO2/SCK4/DACK2/ IRQ10-B/TRST* 2 /EDACK0-B P37/PO15/TIOCA2/TIOCB2/ TCLKD-A P60/TMRI2/TxD4/DREQ2/ IRQ8-B/EDREQ0-B P61/TMCI2/RxD4/TEND2/ IRQ9-B/ETEND0-B P62/TMO2/SCK4/DACK2/ IRQ10-B/EDACK0-B 110 PLLVcc PLLVcc PLLVcc 111 P63/TMRI3/DREQ3/ IRQ11-B/EDREQ1-B P63/TMRI3/DREQ3/ IRQ11-B/TMS* 2 /EDREQ1-B P63/TMRI3/DREQ3/ IRQ11-B/EDREQ1-B 112 PLLVss PLLVss PLLVss 113 P64/TMCI3/TEND3/ETEND1-B P64/TMCI3/TEND3/TDI* 2 /ETEND1-B P64/TMCI3/TEND3/ETEND1-B 114 P65/TMO3/DACK3/EDACK1-B P65/TMO3/DACK3/TCK* 2 /EDACK1-B P65/TMO3/DACK3/EDACK1-B 115 MD0 MD0 MD0 116 PC2/LUCAS/DQMLU PC2/LUCAS/DQMLU PC2/LUCAS/DQMLU 117 PC3/LLCAS/DQMLL PC3/LLCAS/DQMLL PC3/LLCAS/DQMLL 118 P50/AN0/IRQ0-B P50/AN0/IRQ0-B P50/AN0/IRQ0-B 119 P51/AN1/IRQ1-B P51/AN1/IRQ1-B P51/AN1/IRQ1-B 120 P52/AN2/IRQ2-B P52/AN2/IRQ2-B P52/AN2/IRQ2-B 121 AVcc AVcc AVcc 122 P53/AN3/IRQ3-B P53/AN3/IRQ3-B P53/AN3/IRQ3-B 123 AVss AVss AVss 124 P54/AN4/IRQ4-B P54/AN4/IRQ4-B P54/AN4/IRQ4-B 125 Vref Vref Vref 126 P55/AN5/IRQ5-B P55/AN5/IRQ5-B P55/AN5/IRQ5-B Rev. 1.00 Jan. 29, 2010 Page 18 of 1402 REJ09B0597-0100
Section 1 Overview Pin No. Pin Name LQFP- 144 Modes 1, 2, and 6 Modes 3 and 7 Modes 4 and 5 127 P56/AN6/DA0/IRQ6-B P56/AN6/DA0/IRQ6-B P56/AN6/DA0/IRQ6-B 128 P57/AN7/DA1/IRQ7-B P57/AN7/DA1/IRQ7-B P57/AN7/DA1/IRQ7-B 129 MD1 MD1 MD1 130 PB4/CS4-B/WE PB4/CS4-B/WE PB4/CS4-B/WE 131 PB5/CS5-D/OE/CKE PB5/CS5-D/OE/CKE PB5/CS5-D/OE/CKE 132 PB6/CS6-D/ (RD/WR-B)/ADTRG0-B PB6/CS6-D/(RD/WR-B)/ADTRG0-B PB6/CS6-D/(RD/WR-B)/ ADTRG0-B 133 MD3 MD3 MD3 134 PA0/BREQO/BS-A PA0/BREQO/BS-A PA0/BREQO/BS-A 135 PA1/BACK/(RD/WR-A) PA1/BACK/(RD/WR-A) PA1/BACK/(RD/WR-A) 136 PA2/BREQ/WAIT PA2/BREQ/WAIT PA2/BREQ/WAIT 137 PA3/LLWR/LLB PA3/LLWR/LLB LLWR/LLB 138 PA4/LHWR/LUB PA4/LHWR/LUB PA4/LHWR/LUB 139 PA5/RD PA5/RD RD 140 PA6/AS/AH/BS-B PA6/AS/AH/BS-B PA6/AS/AH/BS-B 141 Vss Vss Vss 142 PA7/Bφ PA7/Bφ PA7/Bφ 143 Vcc Vcc Vcc 144 PB0/CS0/CS4-A/CS5-B PB0/CS0/CS4-A/CS5-B PB0/CS0/CS4-A/CS5-B ⎯ NC NC NC Notes: 1. These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode. 2. Pins TDO, TRST, TMS, and TCK are enabled in mode 3. Rev. 1.00 Jan. 29, 2010 Page 19 of 1402 REJ09B0597-0100
Page 1 and 2: REJ09B0597-0100 H8SX/1665MZ Group 3
Page 3 and 4: Notes regarding these materials 1.
Page 5 and 6: How to Use This Manual 1. Objective
Page 7 and 8: 3. Description of Registers Each re
Page 9 and 10: Contents Section 1 Overview........
Page 11 and 12: 4.2 Input/Output Pin ..............
Page 13 and 14: 8.3.2 Break Address Mask Register n
Page 15 and 16: 9.10.6 Controlling Column Address O
Page 17 and 18: 11.3.2 EXDMA Destination Address Re
Page 19 and 20: Section 13 I/O Ports...............
Page 21 and 22: 14.10.11 Conflict between Overflow/
Page 23 and 24: Section 18 Watchdog Timer (WDT)....
Page 25 and 26: Section 20 USB Function Module (USB
Page 27 and 28: 21.4.6 Noise Canceler..............
Page 29 and 30: 25.11 Switching between User MAT an
Page 31 and 32: 28.12.2 Current Consumption during
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Page 35 and 36: Section 1 Overview Classification C
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Page 41 and 42: Section 1 Overview Table 1.2 Compar
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Page 61 and 62: Section 2 CPU Section 2 CPU The H8S
Page 63 and 64: Section 2 CPU 2.2 CPU Operating Mod
Page 65 and 66: Section 2 CPU 2.2.2 Middle Mode The
Page 67 and 68: Section 2 CPU • Stack Structure T
Page 69 and 70: Section 2 CPU 2.3 Instruction Fetch
Page 71 and 72: Section 2 CPU 2.5.1 General Registe
Page 73 and 74: Section 2 CPU 2.5.3 Condition-Code
Page 75 and 76: Section 2 CPU 2.5.5 Vector Base Reg
Page 77 and 78: Section 2 CPU 2.6.2 Memory Data For
Page 79 and 80: Section 2 CPU Function Instructions
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Page 83 and 84: Section 2 CPU Table 2.2 Combination
Page 85 and 86: Section 2 CPU Table 2.4 Data Transf
Page 87 and 88: Section 2 CPU Table 2.6 Arithmetic
Page 89 and 90: Section 2 CPU Table 2.7 Logic Opera
Page 91 and 92: Section 2 CPU Instruction Size Func
Page 93 and 94: Section 2 CPU Table 2.11 System Con
Page 95 and 96: Section 2 CPU 2.8 Addressing Modes
Page 97 and 98: Section 2 CPU 2.8.5 Register Indire
Page 99 and 100: Section 2 CPU 2.8.7 Immediate—#xx
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Section 2 CPU 2.8.11 Extended Memor
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Section 2 CPU Table 2.15 Effective
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Section 2 CPU Request for exception
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Section 3 MCU Operating Modes Secti
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Section 3 MCU Operating Modes 3.2 R
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Section 3 MCU Operating Modes 3.2.2
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Section 3 MCU Operating Modes 3.3 O
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Section 3 MCU Operating Modes 3.3.8
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Section 3 MCU Operating Modes H'000
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Section 4 Resets Section 4 Resets 4
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Section 4 Resets Note that some reg
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Section 4 Resets Bit Bit Name Initi
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Section 4 Resets 4.4 Pin Reset This
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Section 4 Resets 4.7 Deep Software
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Section 5 Voltage Detection Circuit
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Section 6 Exception Handling Sectio
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Section 6 Exception Handling Vector
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Section 6 Exception Handling 6.3.2
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Section 6 Exception Handling 6.4 Tr
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Section 6 Exception Handling Bus Cy
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Section 6 Exception Handling 6.6 In
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Section 6 Exception Handling 6.7 In
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Section 6 Exception Handling 6.7.3
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Section 6 Exception Handling 6.9 Us
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Section 7 Interrupt Controller Sect
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Section 7 Interrupt Controller 7.2
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Section 7 Interrupt Controller 7.3.
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Section 7 Interrupt Controller Bit
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Tabl
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Section 7 Interrupt Controller (2)
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Section 7 Interrupt Controller The
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Section 8 User Break Controller (UB
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Section 9 Bus Controller (BSC) Sect
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Section 9 Bus Controller (BSC) 9.2.
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Section 9 Bus Controller (BSC) Bit
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Section 9 Bus Controller (BSC) Bus
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Section 9 Bus Controller (BSC) Divi
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Section 9 Bus Controller (BSC) Name
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Section 9 Bus Controller (BSC) Area
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Section 9 Bus Controller (BSC) (4)
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Section 9 Bus Controller (BSC) Numb
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Section 10 DMA Controller (DMAC) Se
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Section 10 DMA Controller (DMAC) (2
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Section 10 DMA Controller (DMAC) TS
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Section 11 EXDMA Controller (EXDMAC
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Section 12 Data Transfer Controller
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Section 13 I/O Ports Section 13 I/O
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Section 13 I/O Ports Function Port
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Section 13 I/O Ports 13.1 Register
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Section 13 I/O Ports 13.1.2 Data Re
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Section 13 I/O Ports 13.1.5 Pull-Up
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Section 13 I/O Ports 13.2 Output Bu
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Section 13 I/O Ports (4) P14/DREQ1-
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Section 13 I/O Ports (8) P10/DREQ0-
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Section 13 I/O Ports (4) P24/PO4/TI
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Section 13 I/O Ports (4) P34/PO12/T
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Section 13 I/O Ports (3) P63/TMRI3/
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Section 13 I/O Ports 13.2.6 Port A
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Section 13 I/O Ports (5) PA3/LLWR/L
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Section 13 I/O Ports 13.2.7 Port B
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Section 13 I/O Ports (5) PB3/CS3/CS
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Section 13 I/O Ports 13.2.8 Port C
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Section 13 I/O Ports (1) PE7/A15, P
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Section 13 I/O Ports (4) PF4/A20 Th
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Section 13 I/O Ports (8) PF0/A16 Th
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Section 13 I/O Ports 13.2.14 Port J
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Section 13 I/O Ports (5) PJ3 The pi
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Section 13 I/O Ports 13.2.15 Port K
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Section 13 I/O Ports (5) PK3 The pi
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Section 13 I/O Ports 13.2.16 Port M
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Section 13 I/O Ports Table 13.5 Ava
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Section 13 I/O Ports Port P2 0 P3 7
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Section 13 I/O Ports Port Output Sp
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Section 13 I/O Ports Port PB PC PD
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Section 13 I/O Ports Port PI PM Out
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Section 13 I/O Ports Bit Bit Name I
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Section 13 I/O Ports 13.4 Usage Not
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Section 14 16-Bit Timer Pulse Unit
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Section 16 8-Bit Timers (TMR) Secti
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Section 16 8-Bit Timers (TMR) Clock
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Section 16 8-Bit Timers (TMR) 16.3
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Section 16 8-Bit Timers (TMR) 16.3.
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Section 16 8-Bit Timers (TMR) Bit B
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Pφ E
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Section 17 32K Timer (TM32K) Sectio
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Section 17 32K Timer (TM32K) 17.3 O
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Section 17 32K Timer (TM32K) To ave
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Section 17 32K Timer (TM32K) 17.5 U
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Section 18 Watchdog Timer (WDT) Sec
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Section 18 Watchdog Timer (WDT) 18.
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Section 18 Watchdog Timer (WDT) H'F
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Section 19 Serial Communication Int
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Section 22 A/D Converter Section 22
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Section 22 A/D Converter Set* ADIE
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Section 22 A/D Converter Table 22.3
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Section 22 A/D Converter Pφ ADTRG0
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Section 22 A/D Converter 22.6 A/D C
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Section 22 A/D Converter 22.7 Usage
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Section 23 D/A Converter Section 23
Page 1107 and 1108:
Section 23 D/A Converter 23.3.1 D/A
Page 1109 and 1110:
Section 23 D/A Converter 23.3.5 D/A
Page 1111 and 1112:
Section 23 D/A Converter 23.4 Opera
Page 1113 and 1114:
Section 23 D/A Converter 23.5 Usage
Page 1115 and 1116:
Section 24 RAM Section 24 RAM This
Page 1117 and 1118:
Section 25 Flash Memory Section 25
Page 1119 and 1120:
Section 25 Flash Memory 25.2 Mode T
Page 1121 and 1122:
Section 25 Flash Memory 25.3 Memory
Page 1123 and 1124:
Section 25 Flash Memory 25.5 Progra
Page 1125 and 1126:
Section 25 Flash Memory 25.6 Input/
Page 1127 and 1128:
Section 25 Flash Memory Table 25.3
Page 1129 and 1130:
Section 25 Flash Memory Bit Bit Nam
Page 1131 and 1132:
Section 25 Flash Memory (2) Flash P
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Section 25 Flash Memory (5) Flash M
Page 1135 and 1136:
Section 25 Flash Memory 25.7.2 Prog
Page 1137 and 1138:
Section 25 Flash Memory (2) Downloa
Page 1139 and 1140:
Section 25 Flash Memory (b) Program
Page 1141 and 1142:
Section 25 Flash Memory (c) Erasure
Page 1143 and 1144:
Section 25 Flash Memory Bit Bit Nam
Page 1145 and 1146:
Section 25 Flash Memory (6) Flash M
Page 1147 and 1148:
Section 25 Flash Memory 25.7.3 RAM
Page 1149 and 1150:
Section 25 Flash Memory 25.8.1 Boot
Page 1151 and 1152:
Section 25 Flash Memory (2) State T
Page 1153 and 1154:
Section 25 Flash Memory 25.8.2 USB
Page 1155 and 1156:
Section 25 Flash Memory (2) State T
Page 1157 and 1158:
Section 25 Flash Memory 25.8.3 User
Page 1159 and 1160:
Section 25 Flash Memory (2) Program
Page 1161 and 1162:
Section 25 Flash Memory ⎯ The ret
Page 1163 and 1164:
Section 25 Flash Memory ⎯ Example
Page 1165 and 1166:
Section 25 Flash Memory The procedu
Page 1167 and 1168:
Section 25 Flash Memory In figure 2
Page 1169 and 1170:
Section 25 Flash Memory In user boo
Page 1171 and 1172:
Section 25 Flash Memory Memory MAT
Page 1173 and 1174:
Page 1175 and 1176:
Page 1177 and 1178:
Section 25 Flash Memory 25.9 Protec
Page 1179 and 1180:
Section 25 Flash Memory Error prote
Page 1181 and 1182:
Section 25 Flash Memory Figure 25.2
Page 1183 and 1184:
Section 25 Flash Memory 25.11 Switc
Page 1185 and 1186:
Section 25 Flash Memory 3. Programm
Page 1187 and 1188:
Section 25 Flash Memory 5. Memory r
Page 1189 and 1190:
Section 25 Flash Memory The selecti
Page 1191 and 1192:
Section 25 Flash Memory (d) Clock M
Page 1193 and 1194:
Section 25 Flash Memory (f) Operati
Page 1195 and 1196:
Section 25 Flash Memory • Area-la
Page 1197 and 1198:
Section 25 Flash Memory Error Respo
Page 1199 and 1200:
Section 25 Flash Memory (5) Transit
Page 1201 and 1202:
Section 25 Flash Memory (8) Program
Page 1203 and 1204:
Section 25 Flash Memory • Erasure
Page 1205 and 1206:
Section 25 Flash Memory (c) 128-Byt
Page 1207 and 1208:
Section 25 Flash Memory (e) Block E
Page 1209 and 1210:
Section 25 Flash Memory (g) User Bo
Page 1211 and 1212:
Section 25 Flash Memory (k) Boot Pr
Page 1213 and 1214:
Section 25 Flash Memory 25.14 Usage
Page 1215 and 1216:
Section 26 Boundary Scan Section 26
Page 1217 and 1218:
Section 26 Boundary Scan 26.4 Regis
Page 1219 and 1220:
Section 26 Boundary Scan Table 26.3
Page 1221 and 1222:
Section 26 Boundary Scan Pin No Pin
Page 1223 and 1224:
Section 26 Boundary Scan Pin No Pin
Page 1225 and 1226:
Section 26 Boundary Scan 26.4.4 IDC
Page 1227 and 1228:
Section 26 Boundary Scan 26.5.2 Com
Page 1229 and 1230:
Section 26 Boundary Scan 26.6 Usage
Page 1231 and 1232:
Section 27 Clock Pulse Generator Se
Page 1233 and 1234:
Section 27 Clock Pulse Generator 27
Page 1235 and 1236:
Section 27 Clock Pulse Generator Bi
Page 1237 and 1238:
Page 1239 and 1240:
Page 1241 and 1242:
Page 1243 and 1244:
Section 27 Clock Pulse Generator Fi
Page 1245 and 1246:
Section 28 Power-Down Modes Section
Page 1247 and 1248:
Section 28 Power-Down Modes Notes:
Page 1249 and 1250:
Section 28 Power-Down Modes 28.2 Re
Page 1251 and 1252:
Section 28 Power-Down Modes Bit Bit
Page 1253 and 1254:
Section 28 Power-Down Modes • MST
Page 1255 and 1256:
Section 28 Power-Down Modes • MST
Page 1257 and 1258:
Section 28 Power-Down Modes Bit 7 6
Page 1259 and 1260:
Page 1261 and 1262:
Section 28 Power-Down Modes 28.2.6
Page 1263 and 1264:
Page 1265 and 1266:
Page 1267 and 1268:
Page 1269 and 1270:
Section 28 Power-Down Modes 28.3 Mu
Page 1271 and 1272:
Section 28 Power-Down Modes 28.5 Sl
Page 1273 and 1274:
Section 28 Power-Down Modes 28.7 So
Page 1275 and 1276:
Page 1277 and 1278:
Section 28 Power-Down Modes 28.8 De
Page 1279 and 1280:
Section 28 Power-Down Modes 4. Exit
Page 1281 and 1282:
Page 1283 and 1284:
Section 28 Power-Down Modes Oscilla
Page 1285 and 1286:
Section 28 Power-Down Modes (3) Dee
Page 1287 and 1288:
Section 28 Power-Down Modes Clear a
Page 1289 and 1290:
Page 1291 and 1292:
Section 28 Power-Down Modes SLPIE =
Page 1294 and 1295:
Section 28 Power-Down Modes 28.12 U
Page 1296 and 1297:
Section 28 Power-Down Modes Rev. 1.
Page 1298 and 1299:
Section 29 List of Registers 29.1 R
Page 1300 and 1301:
Section 29 List of Registers Access
Page 1302 and 1303:
Page 1304 and 1305:
Page 1306 and 1307:
Page 1308 and 1309:
Page 1310 and 1311:
Page 1312 and 1313:
Page 1314 and 1315:
Section 29 List of Registers 29.2 R
Page 1316 and 1317:
Section 29 List of Registers Regist
Page 1318 and 1319:
Page 1320 and 1321:
Page 1322 and 1323:
Page 1324 and 1325:
Page 1326 and 1327:
Page 1328 and 1329:
Page 1330 and 1331:
Page 1332 and 1333:
Page 1334 and 1335:
Page 1336 and 1337:
Page 1338 and 1339:
Page 1340 and 1341:
Section 29 List of Registers Notes:
Page 1342 and 1343:
Page 1344 and 1345:
Page 1346 and 1347:
Page 1348 and 1349:
Page 1350 and 1351:
Page 1352 and 1353:
Page 1354 and 1355:
Page 1356 and 1357:
Page 1358 and 1359:
Section 29 List of Registers Rev. 1
Page 1360 and 1361:
Section 30 Electrical Characteristi
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Page 1366 and 1367:
Page 1368 and 1369:
Page 1370 and 1371:
Page 1372 and 1373:
Page 1374 and 1375:
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Page 1378 and 1379:
Page 1380 and 1381:
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Page 1384 and 1385:
Page 1386 and 1387:
t WDD t WDS2 t WDH3 Section 30 Elec
Page 1388 and 1389:
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Page 1394 and 1395:
Page 1396 and 1397:
Page 1398 and 1399:
Page 1400 and 1401:
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Page 1408 and 1409:
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Page 1412 and 1413:
Page 1414 and 1415:
Page 1416 and 1417:
Page 1418 and 1419:
Appendix Port Name PA2/ BREQ/ WAIT
Page 1420 and 1421:
Appendix Port Name PB6/ CS6-D/ (RD/
Page 1422 and 1423:
Appendix B. Product Lineup Product
Page 1424 and 1425:
Appendix D. Treatment of Unused Pin
Page 1426 and 1427:
Appendix Rev. 1.00 Jan. 29, 2010 Pa
Page 1428 and 1429:
Cluster transfer modes.............
Page 1430 and 1431:
P Package dimensions...............
Page 1432 and 1433:
PODRH .............................
Page 1434 and 1435:
Rev. 1.00 Jan. 29, 2010 Page 1402 o
Page 1436:
Sales Strategic Planning Div. Nippo
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H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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