H8SX/1665MZ Group Hardware Manual - Renesas Electronics

9.17 Bus Controller Operation in Reset.................................................................................... 365
9.18 Usage Notes...................................................................................................................... 365
Section 10 DMA Controller (DMAC)...............................................................369
10.1 Features............................................................................................................................. 369
10.2 Input/Output Pins.............................................................................................................. 372
10.3 Register Descriptions........................................................................................................ 373
10.3.1 DMA Source Address Register (DSAR) .......................................................... 374
10.3.2 DMA Destination Address Register (DDAR) .................................................. 375
10.3.3 DMA Offset Register (DOFR).......................................................................... 376
10.3.4 DMA Transfer Count Register (DTCR) ........................................................... 377
10.3.5 DMA Block Size Register (DBSR) .................................................................. 378
10.3.6 DMA Mode Control Register (DMDR)............................................................ 379
10.3.7 DMA Address Control Register (DACR)......................................................... 388
10.3.8 DMA Module Request Select Register (DMRSR) ........................................... 394
10.4 Transfer Modes................................................................................................................. 395
10.5 Operations......................................................................................................................... 396
10.5.1 Address Modes ................................................................................................. 396
10.5.2 Transfer Modes................................................................................................. 400
10.5.3 Activation Sources............................................................................................ 405
10.5.4 Bus Access Modes............................................................................................ 407
10.5.5 Extended Repeat Area Function ....................................................................... 409
10.5.6 Address Update Function using Offset ............................................................. 412
10.5.7 Register during DMA Transfer......................................................................... 416
10.5.8 Priority of Channels.......................................................................................... 421
10.5.9 DMA Basic Bus Cycle...................................................................................... 423
10.5.10 Bus Cycles in Dual Address Mode ................................................................... 424
10.5.11 Bus Cycles in Single Address Mode................................................................. 433
10.6 DMA Transfer End ........................................................................................................... 438
10.7 Relationship among DMAC and Other Bus Masters........................................................ 441
10.7.1 CPU Priority Control Function Over DMAC ................................................... 441
10.7.2 Bus Arbitration among DMAC and Other Bus Masters ................................... 442
10.8 Interrupt Sources...............................................................................................................443
10.9 Usage Notes...................................................................................................................... 446
Section 11 EXDMA Controller (EXDMAC)....................................................447
11.1 Features............................................................................................................................. 447
11.2 Input/Output Pins.............................................................................................................. 450
11.3 Registers Descriptions ...................................................................................................... 451
11.3.1 EXDMA Source Address Register (EDSAR)................................................... 452
Rev. 1.00 Jan. 29, 2010 Page xvi of xxxii