H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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19.4.5 Serial Data Transmission (Asynchronous Mode) ............................................. 886 19.4.6 Serial Data Reception (Asynchronous Mode) .................................................. 888 19.5 Multiprocessor Communication Function ........................................................................ 892 19.5.1 Multiprocessor Serial Data Transmission......................................................... 894 19.5.2 Multiprocessor Serial Data Reception .............................................................. 895 19.6 Operation in Clocked Synchronous Mode (SCI_0, 1, and 4 only) ................................... 898 19.6.1 Clock................................................................................................................. 898 19.6.2 SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, and 4 only) ......... 899 19.6.3 Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, and 4 only)....................................................................................... 900 19.6.4 Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, and 4 only)....................................................................................... 902 19.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0, 1, and 4 only) ...................................... 903 19.7 Operation in Smart Card Interface Mode.......................................................................... 905 19.7.1 Sample Connection........................................................................................... 905 19.7.2 Data Format (Except in Block Transfer Mode) ................................................ 906 19.7.3 Block Transfer Mode........................................................................................ 907 19.7.4 Receive Data Sampling Timing and Reception Margin ................................... 908 19.7.5 Initialization...................................................................................................... 909 19.7.6 Data Transmission (Except in Block Transfer Mode) ...................................... 910 19.7.7 Serial Data Reception (Except in Block Transfer Mode) ................................. 913 19.7.8 Clock Output Control (Only SCI_0, 1, and 4) .................................................. 914 19.8 Interrupt Sources...............................................................................................................916 19.8.1 Interrupts in Normal Serial Communication Interface Mode ........................... 916 19.8.2 Interrupts in Smart Card Interface Mode .......................................................... 917 19.9 Usage Notes...................................................................................................................... 919 19.9.1 Module Stop Function Setting .......................................................................... 919 19.9.2 Break Detection and Processing ....................................................................... 919 19.9.3 Mark State and Break Detection....................................................................... 919 19.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only).................................................................. 919 19.9.5 Relation between Writing to TDR and TDRE Flag.......................................... 920 19.9.6 Restrictions on Using DTC or DMAC.............................................................. 920 19.9.7 SCI Operations during Power-Down State ....................................................... 921 19.10 CRC Operation Circuit ..................................................................................................... 924 19.10.1 Features............................................................................................................. 924 19.10.2 Register Descriptions........................................................................................ 925 19.10.3 CRC Operation Circuit Operation .................................................................... 927 19.10.4 Note on CRC Operation Circuit........................................................................ 930 Rev. 1.00 Jan. 29, 2010 Page xxiv of xxxii
Section 20 USB Function Module (USB)..........................................................931 20.1 Features............................................................................................................................. 931 20.2 Input/Output Pins.............................................................................................................. 932 20.3 Register Descriptions........................................................................................................ 933 20.3.1 Interrupt Flag Register 0 (IFR0) ....................................................................... 934 20.3.2 Interrupt Flag Register 1 (IFR1) ....................................................................... 936 20.3.3 Interrupt Flag Register 2 (IFR2) ....................................................................... 937 20.3.4 Interrupt Select Register 0 (ISR0)..................................................................... 939 20.3.5 Interrupt Select Register 1 (ISR1)..................................................................... 940 20.3.6 Interrupt Select Register 2 (ISR2)..................................................................... 941 20.3.7 Interrupt Enable Register 0 (IER0) ................................................................... 942 20.3.8 Interrupt Enable Register 1 (IER1) ................................................................... 943 20.3.9 Interrupt Enable Register 2 (IER2) ................................................................... 943 20.3.10 EP0i Data Register (EPDR0i)........................................................................... 944 20.3.11 EP0o Data Register (EPDR0o) ......................................................................... 945 20.3.12 EP0s Data Register (EPDR0s) .......................................................................... 945 20.3.13 EP1 Data Register (EPDR1) ............................................................................. 946 20.3.14 EP2 Data Register (EPDR2) ............................................................................. 946 20.3.15 EP3 Data Register (EPDR3) ............................................................................. 947 20.3.16 EP0o Receive Data Size Register (EPSZ0o) .................................................... 947 20.3.17 EP1 Receive Data Size Register (EPSZ1) ........................................................ 948 20.3.18 Trigger Register (TRG)..................................................................................... 948 20.3.19 Data Status Register (DASTS).......................................................................... 950 20.3.20 FIFO Clear Register (FCLR) ............................................................................ 951 20.3.21 DMA Transfer Setting Register (DMA) ........................................................... 952 20.3.22 Endpoint Stall Register (EPSTL)...................................................................... 955 20.3.23 Configuration Value Register (CVR) ............................................................... 956 20.3.24 Control Register (CTLR) .................................................................................. 956 20.3.25 Endpoint Information Register (EPIR) ............................................................. 958 20.3.26 Transceiver Test Register 0 (TRNTREG0)....................................................... 962 20.3.27 Transceiver Test Register 1 (TRNTREG1)....................................................... 964 20.4 Interrupt Sources...............................................................................................................966 20.5 Operation .......................................................................................................................... 968 20.5.1 Cable Connection.............................................................................................. 968 20.5.2 Cable Disconnection ......................................................................................... 969 20.5.3 Suspend and Resume Operations...................................................................... 969 20.5.4 Control Transfer................................................................................................ 977 20.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)............................................................... 983 20.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ................................................................. 984 20.5.7 EP3 Interrupt-In Transfer.................................................................................. 985 Rev. 1.00 Jan. 29, 2010 Page xxv of xxxii
Page 1 and 2: REJ09B0597-0100 H8SX/1665MZ Group 3
Page 3 and 4: Notes regarding these materials 1.
Page 5 and 6: How to Use This Manual 1. Objective
Page 7 and 8: 3. Description of Registers Each re
Page 9 and 10: Contents Section 1 Overview........
Page 11 and 12: 4.2 Input/Output Pin ..............
Page 13 and 14: 8.3.2 Break Address Mask Register n
Page 15 and 16: 9.10.6 Controlling Column Address O
Page 17 and 18: 11.3.2 EXDMA Destination Address Re
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Page 21 and 22: 14.10.11 Conflict between Overflow/
Page 23: Section 18 Watchdog Timer (WDT)....
Page 27 and 28: 21.4.6 Noise Canceler..............
Page 29 and 30: 25.11 Switching between User MAT an
Page 31 and 32: 28.12.2 Current Consumption during
Page 33 and 34: Section 1 Overview Section 1 Overvi
Page 35 and 36: Section 1 Overview Classification C
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Page 41 and 42: Section 1 Overview Table 1.2 Compar
Page 43 and 44: Section 1 Overview Part No. R 5 F 6
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Page 47 and 48: Section 1 Overview Pin No. Pin Name
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Page 61 and 62: Section 2 CPU Section 2 CPU The H8S
Page 63 and 64: Section 2 CPU 2.2 CPU Operating Mod
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Page 67 and 68: Section 2 CPU • Stack Structure T
Page 69 and 70: Section 2 CPU 2.3 Instruction Fetch
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Section 2 CPU 2.5.5 Vector Base Reg
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Section 2 CPU 2.6.2 Memory Data For
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Section 2 CPU Function Instructions
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Section 2 CPU Classification Instru
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Section 2 CPU Table 2.2 Combination
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Section 2 CPU Table 2.4 Data Transf
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Section 2 CPU Table 2.6 Arithmetic
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Section 2 CPU Table 2.7 Logic Opera
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Section 2 CPU Instruction Size Func
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Section 2 CPU Table 2.11 System Con
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Section 2 CPU 2.8 Addressing Modes
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Section 2 CPU 2.8.5 Register Indire
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Section 2 CPU 2.8.7 Immediate—#xx
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Section 2 CPU 2.8.11 Extended Memor
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Section 2 CPU Table 2.15 Effective
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Section 2 CPU Request for exception
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Section 3 MCU Operating Modes Secti
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Section 3 MCU Operating Modes 3.2 R
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Section 3 MCU Operating Modes 3.2.2
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Section 3 MCU Operating Modes 3.3 O
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Section 3 MCU Operating Modes 3.3.8
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Section 3 MCU Operating Modes H'000
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Section 4 Resets Section 4 Resets 4
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Section 4 Resets Note that some reg
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Section 4 Resets Bit Bit Name Initi
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Section 4 Resets 4.4 Pin Reset This
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Section 4 Resets 4.7 Deep Software
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Section 5 Voltage Detection Circuit
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Section 6 Exception Handling Sectio
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Section 6 Exception Handling Vector
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Section 6 Exception Handling 6.3.2
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Section 6 Exception Handling 6.4 Tr
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Section 6 Exception Handling Bus Cy
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Section 6 Exception Handling 6.6 In
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Section 6 Exception Handling 6.7 In
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Section 6 Exception Handling 6.7.3
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Section 6 Exception Handling 6.9 Us
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Section 7 Interrupt Controller Sect
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Section 7 Interrupt Controller 7.2
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Section 7 Interrupt Controller 7.3.
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Section 7 Interrupt Controller Bit
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Vect
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Section 7 Interrupt Controller Tabl
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Section 7 Interrupt Controller (2)
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Section 7 Interrupt Controller The
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Section 8 User Break Controller (UB
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Section 9 Bus Controller (BSC) Sect
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Section 9 Bus Controller (BSC) A bl
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Section 9 Bus Controller (BSC) 9.2.
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Section 9 Bus Controller (BSC) Bit
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Section 9 Bus Controller (BSC) Bus
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Section 9 Bus Controller (BSC) 9.4
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Section 9 Bus Controller (BSC) Divi
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Section 9 Bus Controller (BSC) Name
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Section 9 Bus Controller (BSC) Area
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Section 9 Bus Controller (BSC) (4)
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Section 9 Bus Controller (BSC) Numb
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Section 9 Bus Controller (BSC) Wait
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Section 9 Bus Controller (BSC) (b)
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Section 10 DMA Controller (DMAC) Se
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Section 10 DMA Controller (DMAC) A
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Section 10 DMA Controller (DMAC) 10
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Bi
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Section 10 DMA Controller (DMAC) Ta
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Section 10 DMA Controller (DMAC) Ad
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Section 10 DMA Controller (DMAC) (2
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Section 10 DMA Controller (DMAC) Th
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Section 10 DMA Controller (DMAC) In
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Section 10 DMA Controller (DMAC) DM
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Section 10 DMA Controller (DMAC) TS
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Section 11 EXDMA Controller (EXDMAC
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Section 12 Data Transfer Controller
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Section 13 I/O Ports Section 13 I/O
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Section 13 I/O Ports Function Port
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Section 13 I/O Ports 13.1 Register
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Section 13 I/O Ports 13.1.2 Data Re
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Section 13 I/O Ports 13.1.5 Pull-Up
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Section 13 I/O Ports 13.2 Output Bu
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Section 13 I/O Ports (4) P14/DREQ1-
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Section 13 I/O Ports (8) P10/DREQ0-
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Section 13 I/O Ports (4) P24/PO4/TI
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Section 13 I/O Ports (4) P34/PO12/T
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Section 13 I/O Ports (3) P63/TMRI3/
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Section 13 I/O Ports 13.2.6 Port A
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Section 13 I/O Ports (5) PA3/LLWR/L
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Section 13 I/O Ports 13.2.7 Port B
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Section 13 I/O Ports (5) PB3/CS3/CS
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Section 13 I/O Ports 13.2.8 Port C
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Section 13 I/O Ports (1) PE7/A15, P
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Section 13 I/O Ports (4) PF4/A20 Th
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Section 13 I/O Ports (8) PF0/A16 Th
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Section 13 I/O Ports 13.2.14 Port J
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Section 13 I/O Ports (5) PJ3 The pi
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Section 13 I/O Ports 13.2.15 Port K
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Section 13 I/O Ports (5) PK3 The pi
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Section 13 I/O Ports 13.2.16 Port M
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Section 13 I/O Ports Table 13.5 Ava
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Section 13 I/O Ports Port P2 0 P3 7
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Section 13 I/O Ports Port Output Sp
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Section 13 I/O Ports Port PB PC PD
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Section 13 I/O Ports Port PI PM Out
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Section 13 I/O Ports Bit Bit Name I
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Section 13 I/O Ports 13.3.6 Port Fu
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Section 13 I/O Ports 13.3.10 Port F
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Section 13 I/O Ports 13.4 Usage Not
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Section 14 16-Bit Timer Pulse Unit
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Section 16 8-Bit Timers (TMR) Secti
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Section 16 8-Bit Timers (TMR) Inter
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Section 16 8-Bit Timers (TMR) Clock
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Section 16 8-Bit Timers (TMR) 16.3
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Section 16 8-Bit Timers (TMR) 16.3.
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Section 16 8-Bit Timers (TMR) Bit B
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Table
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Bit 1
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Section 16 8-Bit Timers (TMR) Pφ E
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Section 17 32K Timer (TM32K) Sectio
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Section 17 32K Timer (TM32K) Bit Bi
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Section 17 32K Timer (TM32K) 17.3 O
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Section 17 32K Timer (TM32K) To ave
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Section 17 32K Timer (TM32K) 17.5 U
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Section 18 Watchdog Timer (WDT) Sec
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Section 18 Watchdog Timer (WDT) 18.
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Section 18 Watchdog Timer (WDT) H'F
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Section 19 Serial Communication Int
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Section 22 A/D Converter Section 22
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Section 22 A/D Converter Module dat
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Section 22 A/D Converter Set* ADIE
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Section 22 A/D Converter 22.4.3 Inp
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Section 22 A/D Converter Table 22.3
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Section 22 A/D Converter Pφ ADTRG0
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Section 23 D/A Converter Section 23
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Section 23 D/A Converter 23.3.1 D/A
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Section 23 D/A Converter 23.3.5 D/A
Page 1111 and 1112:
Section 23 D/A Converter 23.4 Opera
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Section 23 D/A Converter 23.5 Usage
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Section 24 RAM Section 24 RAM This
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Section 25 Flash Memory Section 25
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Section 25 Flash Memory 25.2 Mode T
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Section 25 Flash Memory 25.3 Memory
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Section 25 Flash Memory 25.5 Progra
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Section 25 Flash Memory 25.6 Input/
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Section 25 Flash Memory Table 25.3
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Section 25 Flash Memory Bit Bit Nam
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Section 25 Flash Memory (2) Flash P
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Section 25 Flash Memory (5) Flash M
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Section 25 Flash Memory 25.7.2 Prog
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Section 25 Flash Memory (2) Downloa
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Section 25 Flash Memory (b) Program
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Section 25 Flash Memory (c) Erasure
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Section 25 Flash Memory Bit Bit Nam
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Section 25 Flash Memory (6) Flash M
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Section 25 Flash Memory 25.7.3 RAM
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Section 25 Flash Memory 25.8.1 Boot
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Section 25 Flash Memory (2) State T
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Section 25 Flash Memory 25.8.2 USB
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Section 25 Flash Memory (2) State T
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Section 25 Flash Memory 25.8.3 User
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Section 25 Flash Memory (2) Program
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Section 25 Flash Memory ⎯ The ret
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Section 25 Flash Memory ⎯ Example
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Section 25 Flash Memory The procedu
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Section 25 Flash Memory In figure 2
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Section 25 Flash Memory In user boo
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Section 25 Flash Memory Memory MAT
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Section 25 Flash Memory 25.9 Protec
Page 1179 and 1180:
Section 25 Flash Memory Error prote
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Section 25 Flash Memory Figure 25.2
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Section 25 Flash Memory 25.11 Switc
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Section 25 Flash Memory 3. Programm
Page 1187 and 1188:
Section 25 Flash Memory 5. Memory r
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Section 25 Flash Memory The selecti
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Section 25 Flash Memory (d) Clock M
Page 1193 and 1194:
Section 25 Flash Memory (f) Operati
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Section 25 Flash Memory • Area-la
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Section 25 Flash Memory Error Respo
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Section 25 Flash Memory (5) Transit
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Section 25 Flash Memory (8) Program
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Section 25 Flash Memory • Erasure
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Section 25 Flash Memory (c) 128-Byt
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Section 25 Flash Memory (e) Block E
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Section 25 Flash Memory (g) User Bo
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Section 25 Flash Memory (k) Boot Pr
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Section 25 Flash Memory 25.14 Usage
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Section 26 Boundary Scan Section 26
Page 1217 and 1218:
Section 26 Boundary Scan 26.4 Regis
Page 1219 and 1220:
Section 26 Boundary Scan Table 26.3
Page 1221 and 1222:
Section 26 Boundary Scan Pin No Pin
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Section 26 Boundary Scan Pin No Pin
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Section 26 Boundary Scan 26.4.4 IDC
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Section 26 Boundary Scan 26.5.2 Com
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Section 26 Boundary Scan 26.6 Usage
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Section 27 Clock Pulse Generator Se
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Section 27 Clock Pulse Generator 27
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Section 27 Clock Pulse Generator Bi
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Section 27 Clock Pulse Generator Fi
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Section 28 Power-Down Modes Section
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Section 28 Power-Down Modes Notes:
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Section 28 Power-Down Modes 28.2 Re
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Section 28 Power-Down Modes Bit Bit
Page 1253 and 1254:
Section 28 Power-Down Modes • MST
Page 1255 and 1256:
Section 28 Power-Down Modes • MST
Page 1257 and 1258:
Section 28 Power-Down Modes Bit 7 6
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Section 28 Power-Down Modes 28.2.6
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Section 28 Power-Down Modes 28.3 Mu
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Section 28 Power-Down Modes 28.5 Sl
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Section 28 Power-Down Modes 28.7 So
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Section 28 Power-Down Modes 28.8 De
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Section 28 Power-Down Modes 4. Exit
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Section 28 Power-Down Modes Oscilla
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Section 28 Power-Down Modes (3) Dee
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Section 28 Power-Down Modes Clear a
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Section 28 Power-Down Modes SLPIE =
Page 1294 and 1295:
Section 28 Power-Down Modes 28.12 U
Page 1296 and 1297:
Section 28 Power-Down Modes Rev. 1.
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Section 29 List of Registers 29.1 R
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Section 29 List of Registers Access
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Page 1312 and 1313:
Page 1314 and 1315:
Section 29 List of Registers 29.2 R
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Section 29 List of Registers Regist
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Section 29 List of Registers Notes:
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Page 1352 and 1353:
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Page 1356 and 1357:
Page 1358 and 1359:
Section 29 List of Registers Rev. 1
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Section 30 Electrical Characteristi
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t WDD t WDS2 t WDH3 Section 30 Elec
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Appendix Port Name PA2/ BREQ/ WAIT
Page 1420 and 1421:
Appendix Port Name PB6/ CS6-D/ (RD/
Page 1422 and 1423:
Appendix B. Product Lineup Product
Page 1424 and 1425:
Appendix D. Treatment of Unused Pin
Page 1426 and 1427:
Appendix Rev. 1.00 Jan. 29, 2010 Pa
Page 1428 and 1429:
Cluster transfer modes.............
Page 1430 and 1431:
P Package dimensions...............
Page 1432 and 1433:
PODRH .............................
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Rev. 1.00 Jan. 29, 2010 Page 1402 o
Page 1436:
Sales Strategic Planning Div. Nippo
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H8SX/1665MZ Group Hardware Manual - Renesas Electronics

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