H8SX/1665MZ Group Hardware Manual - Renesas Electronics

More documents

Recommendations

Info

23.2 Input/Output Pins............................................................................................................ 1074 23.3 Register Descriptions...................................................................................................... 1074 23.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ............................................ 1075 23.3.2 D/A Data Registers 0H and 1H (DADR0H and DADR1H) ........................... 1075 23.3.3 D/A Data Registers 0L and 1L (DADR0L and DADR1L)............................. 1076 23.3.4 D/A Data Register 01T (DADR01T).............................................................. 1076 23.3.5 D/A Control Register 01 (DACR01) .............................................................. 1077 23.3.6 Usage as an 8-Bit D/A Converter ................................................................... 1078 23.4 Operation ........................................................................................................................ 1079 23.5 Usage Notes.................................................................................................................... 1081 23.5.1 Module Stop State Setting .............................................................................. 1081 23.5.2 D/A Output Hold Function in Software Standby Mode.................................. 1081 23.5.3 Notes on Deep Software Standby Mode......................................................... 1081 23.5.4 Limitations on Emulators................................................................................ 1081 Section 24 RAM..............................................................................................1083 Section 25 Flash Memory................................................................................1085 25.1 Features........................................................................................................................... 1085 25.2 Mode Transition Diagram............................................................................................... 1087 25.3 Memory MAT Configuration ......................................................................................... 1089 25.4 Block Structure ............................................................................................................... 1090 25.4.1 Block Diagram of <strong>H8SX</strong>/1665........................................................................ 1090 25.5 Programming/Erasing Interface...................................................................................... 1091 25.6 Input/Output Pins............................................................................................................ 1093 25.7 Register Descriptions...................................................................................................... 1094 25.7.1 Programming/Erasing Interface Registers ...................................................... 1096 25.7.2 Programming/Erasing Interface Parameters ................................................... 1103 25.7.3 RAM Emulation Register (RAMER).............................................................. 1115 25.8 On-Board Programming Mode ....................................................................................... 1116 25.8.1 Boot Mode ...................................................................................................... 1117 25.8.2 USB Boot Mode ............................................................................................. 1121 25.8.3 User Program Mode........................................................................................ 1125 25.8.4 User Boot Mode.............................................................................................. 1135 25.8.5 On-Chip Program and Storable Area for Program Data ................................. 1139 25.9 Protection........................................................................................................................ 1145 25.9.1 <strong>Hardware</strong> Protection ....................................................................................... 1145 25.9.2 Software Protection......................................................................................... 1146 25.9.3 Error Protection .............................................................................................. 1146 25.10 Flash Memory Emulation Using RAM........................................................................... 1148 Rev. 1.00 Jan. 29, 2010 Page xxviii of xxxii
25.11 Switching between User MAT and User Boot MAT...................................................... 1151 25.12 Programmer Mode .......................................................................................................... 1152 25.13 Standard Serial Communications Interface Specifications for Boot Mode..................... 1152 25.14 Usage Notes.................................................................................................................... 1181 Section 26 Boundary Scan...............................................................................1183 26.1 Features........................................................................................................................... 1183 26.2 Block Diagram of Boundary Scan Function ................................................................... 1184 26.3 Input/Output Pins............................................................................................................ 1184 26.4 Register Descriptions...................................................................................................... 1185 26.4.1 Instruction Register (JTIR) ............................................................................. 1186 26.4.2 Bypass Register (JTBPR) ............................................................................... 1187 26.4.3 Boundary Scan Register (JTBSR)................................................................... 1187 26.4.4 IDCODE Register (JTID) ............................................................................... 1193 26.5 Operations....................................................................................................................... 1194 26.5.1 TAP Controller ............................................................................................... 1194 26.5.2 Commands ...................................................................................................... 1195 26.6 Usage Notes.................................................................................................................... 1197 Section 27 Clock Pulse Generator ...................................................................1199 27.1 Register Description ....................................................................................................... 1201 27.1.1 System Clock Control Register (SCKCR) ...................................................... 1201 27.1.2 Subclock Control Register (SUBCKCR)........................................................ 1203 27.2 Oscillator......................................................................................................................... 1205 27.2.1 Connecting Crystal Resonator ........................................................................ 1205 27.2.2 External Clock Input....................................................................................... 1206 27.3 PLL Circuit ..................................................................................................................... 1207 27.4 Frequency Divider .......................................................................................................... 1207 27.5 Subclock Oscillator......................................................................................................... 1207 27.5.1 Connecting 32.768 kHz Crystal Resonator..................................................... 1207 27.5.2 Handling of Pins when the Subclock is Not to be Used.................................. 1208 27.6 Usage Notes.................................................................................................................... 1209 27.6.1 Notes on Clock Pulse Generator ..................................................................... 1209 27.6.2 Notes on Resonator......................................................................................... 1210 27.6.3 Notes on Board Design ................................................................................... 1210 Section 28 Power-Down Modes ......................................................................1213 28.1 Features........................................................................................................................... 1213 28.2 Register Descriptions...................................................................................................... 1217 28.2.1 Standby Control Register (SBYCR) ............................................................... 1218 Rev. 1.00 Jan. 29, 2010 Page xxix of xxxii
Page 1 and 2: REJ09B0597-0100 H8SX/1665MZ Group 3
Page 3 and 4: Notes regarding these materials 1.
Page 5 and 6: How to Use This Manual 1. Objective
Page 7 and 8: 3. Description of Registers Each re
Page 9 and 10: Contents Section 1 Overview........
Page 11 and 12: 4.2 Input/Output Pin ..............
Page 13 and 14: 8.3.2 Break Address Mask Register n
Page 15 and 16: 9.10.6 Controlling Column Address O
Page 17 and 18: 11.3.2 EXDMA Destination Address Re
Page 19 and 20: Section 13 I/O Ports...............
Page 21 and 22: 14.10.11 Conflict between Overflow/
Page 23 and 24: Section 18 Watchdog Timer (WDT)....
Page 25 and 26: Section 20 USB Function Module (USB
Page 27: 21.4.6 Noise Canceler..............
Page 31 and 32: 28.12.2 Current Consumption during
Page 33 and 34: Section 1 Overview Section 1 Overvi
Page 35 and 36: Section 1 Overview Classification C
Page 37 and 38: Section 1 Overview Classification E
Page 39 and 40: Section 1 Overview Classification T
Page 41 and 42: Section 1 Overview Table 1.2 Compar
Page 43 and 44: Section 1 Overview Part No. R 5 F 6
Page 45 and 46: Section 1 Overview 1.4 Pin Assignme
Page 47 and 48: Section 1 Overview Pin No. Pin Name
Page 53 and 54: Section 1 Overview Classification P
Page 61 and 62: Section 2 CPU Section 2 CPU The H8S
Page 63 and 64: Section 2 CPU 2.2 CPU Operating Mod
Page 65 and 66: Section 2 CPU 2.2.2 Middle Mode The
Page 67 and 68: Section 2 CPU • Stack Structure T
Page 69 and 70: Section 2 CPU 2.3 Instruction Fetch
Page 71 and 72: Section 2 CPU 2.5.1 General Registe
Page 73 and 74: Section 2 CPU 2.5.3 Condition-Code
Page 75 and 76: Section 2 CPU 2.5.5 Vector Base Reg
Page 77 and 78: Section 2 CPU 2.6.2 Memory Data For
Page 79 and 80:
Section 2 CPU Function Instructions
Page 81 and 82:
Section 2 CPU Classification Instru
Page 83 and 84:
Section 2 CPU Table 2.2 Combination
Page 85 and 86:
Section 2 CPU Table 2.4 Data Transf
Page 87 and 88:
Section 2 CPU Table 2.6 Arithmetic
Page 89 and 90:
Section 2 CPU Table 2.7 Logic Opera
Page 91 and 92:
Section 2 CPU Instruction Size Func
Page 93 and 94:
Section 2 CPU Table 2.11 System Con
Page 95 and 96:
Section 2 CPU 2.8 Addressing Modes
Page 97 and 98:
Section 2 CPU 2.8.5 Register Indire
Page 99 and 100:
Section 2 CPU 2.8.7 Immediate—#xx
Page 101 and 102:
Section 2 CPU 2.8.11 Extended Memor
Page 103 and 104:
Section 2 CPU Table 2.15 Effective
Page 105 and 106:
Section 2 CPU Request for exception
Page 107 and 108:
Section 3 MCU Operating Modes Secti
Page 109 and 110:
Section 3 MCU Operating Modes 3.2 R
Page 111 and 112:
Section 3 MCU Operating Modes 3.2.2
Page 113 and 114:
Section 3 MCU Operating Modes 3.3 O
Page 115 and 116:
Section 3 MCU Operating Modes 3.3.8
Page 117 and 118:
Section 3 MCU Operating Modes H'000
Page 119 and 120:
Section 4 Resets Section 4 Resets 4
Page 121 and 122:
Section 4 Resets Note that some reg
Page 123 and 124:
Section 4 Resets Bit Bit Name Initi
Page 125 and 126:
Section 4 Resets 4.4 Pin Reset This
Page 127 and 128:
Section 4 Resets 4.7 Deep Software
Page 129 and 130:
Section 5 Voltage Detection Circuit
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Section 6 Exception Handling Sectio
Page 139 and 140:
Section 6 Exception Handling Vector
Page 141 and 142:
Section 6 Exception Handling 6.3.2
Page 143 and 144:
Section 6 Exception Handling 6.4 Tr
Page 145 and 146:
Section 6 Exception Handling Bus Cy
Page 147 and 148:
Section 6 Exception Handling 6.6 In
Page 149 and 150:
Section 6 Exception Handling 6.7 In
Page 151 and 152:
Section 6 Exception Handling 6.7.3
Page 153 and 154:
Section 6 Exception Handling 6.9 Us
Page 155 and 156:
Section 7 Interrupt Controller Sect
Page 157 and 158:
Section 7 Interrupt Controller 7.2
Page 159 and 160:
Section 7 Interrupt Controller 7.3.
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Section 7 Interrupt Controller Bit
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Section 7 Interrupt Controller Vect
Page 179 and 180:
Section 7 Interrupt Controller Vect
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Section 7 Interrupt Controller Tabl
Page 189 and 190:
Section 7 Interrupt Controller (2)
Page 191 and 192:
Section 7 Interrupt Controller The
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Section 8 User Break Controller (UB
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Section 9 Bus Controller (BSC) Sect
Page 211 and 212:
Section 9 Bus Controller (BSC) A bl
Page 213 and 214:
Section 9 Bus Controller (BSC) 9.2.
Page 215 and 216:
Page 217 and 218:
Section 9 Bus Controller (BSC) Bit
Page 219 and 220:
Page 221 and 222:
Section 9 Bus Controller (BSC) Bus
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Section 9 Bus Controller (BSC) 9.4
Page 249 and 250:
Section 9 Bus Controller (BSC) Divi
Page 251 and 252:
Page 253 and 254:
Section 9 Bus Controller (BSC) Name
Page 255 and 256:
Page 257 and 258:
Section 9 Bus Controller (BSC) Area
Page 259 and 260:
Section 9 Bus Controller (BSC) (4)
Page 261 and 262:
Section 9 Bus Controller (BSC) Numb
Page 263 and 264:
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Section 9 Bus Controller (BSC) Stro
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Section 9 Bus Controller (BSC) Addr
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Section 9 Bus Controller (BSC) To e
Page 313 and 314:
Page 315 and 316:
Section 9 Bus Controller (BSC) Wait
Page 317 and 318:
Section 9 Bus Controller (BSC) T p
Page 319 and 320:
Page 321 and 322:
Page 323 and 324:
Section 9 Bus Controller (BSC) (b)
Page 325 and 326:
Section 9 Bus Controller (BSC) Pφ
Page 327 and 328:
Page 329 and 330:
Page 331 and 332:
Page 333 and 334:
Page 335 and 336:
Page 337 and 338:
Page 339 and 340:
Page 341 and 342:
Page 343 and 344:
Page 345 and 346:
Page 347 and 348:
Section 9 Bus Controller (BSC) This
Page 349 and 350:
Page 351 and 352:
Section 9 Bus Controller (BSC) SDRA
Page 353 and 354:
Page 355 and 356:
Section 9 Bus Controller (BSC) The
Page 357 and 358:
Page 359 and 360:
Section 9 Bus Controller (BSC) (b)
Page 361 and 362:
Page 363 and 364:
Page 365 and 366:
Page 367 and 368:
Page 369 and 370:
Page 371 and 372:
Section 9 Bus Controller (BSC) A re
Page 373 and 374:
Page 375 and 376:
Page 377 and 378:
Page 379 and 380:
Page 381 and 382:
Page 383 and 384:
Section 9 Bus Controller (BSC) Bφ
Page 385 and 386:
Page 387 and 388:
Section 9 Bus Controller (BSC) •
Page 389 and 390:
Section 9 Bus Controller (BSC) Exte
Page 391 and 392:
Page 393 and 394:
Page 395 and 396:
Page 397 and 398:
Page 399 and 400:
Page 401 and 402:
Section 10 DMA Controller (DMAC) Se
Page 403 and 404:
Section 10 DMA Controller (DMAC) A
Page 405 and 406:
Section 10 DMA Controller (DMAC) 10
Page 407 and 408:
Page 409 and 410:
Page 411 and 412:
Section 10 DMA Controller (DMAC) Ta
Page 413 and 414:
Section 10 DMA Controller (DMAC) Bi
Page 415 and 416:
Page 417 and 418:
Page 419 and 420:
Section 10 DMA Controller (DMAC) In
Page 421 and 422:
Page 423 and 424:
Page 425 and 426:
Section 10 DMA Controller (DMAC) Ta
Page 427 and 428:
Page 429 and 430:
Section 10 DMA Controller (DMAC) Ad
Page 431 and 432:
Section 10 DMA Controller (DMAC) Tr
Page 433 and 434:
Section 10 DMA Controller (DMAC) (2
Page 435 and 436:
Section 10 DMA Controller (DMAC) Fi
Page 437 and 438:
Page 439 and 440:
Page 441 and 442:
Page 443 and 444:
Page 445 and 446:
Section 10 DMA Controller (DMAC) Th
Page 447 and 448:
Section 10 DMA Controller (DMAC) Wh
Page 449 and 450:
Section 10 DMA Controller (DMAC) In
Page 451 and 452:
Page 453 and 454:
Page 455 and 456:
Page 457 and 458:
Section 10 DMA Controller (DMAC) DM
Page 459 and 460:
Page 461 and 462:
Page 463 and 464:
Page 465 and 466:
Page 467 and 468:
Page 469 and 470:
Page 471 and 472:
Page 473 and 474:
Page 475 and 476:
Page 477 and 478:
Section 10 DMA Controller (DMAC) TS
Page 479 and 480:
Section 11 EXDMA Controller (EXDMAC
Page 481 and 482:
Page 483 and 484:
Page 485 and 486:
Page 487 and 488:
Page 489 and 490:
Page 491 and 492:
Page 493 and 494:
Page 495 and 496:
Page 497 and 498:
Page 499 and 500:
Page 501 and 502:
Page 503 and 504:
Page 505 and 506:
Page 507 and 508:
Page 509 and 510:
Page 511 and 512:
Page 513 and 514:
Page 515 and 516:
Page 517 and 518:
Page 519 and 520:
Page 521 and 522:
Page 523 and 524:
Page 525 and 526:
Page 527 and 528:
Page 529 and 530:
Page 531 and 532:
Page 533 and 534:
Page 535 and 536:
Page 537 and 538:
Page 539 and 540:
Page 541 and 542:
Page 543 and 544:
Page 545 and 546:
Page 547 and 548:
Page 549 and 550:
Page 551 and 552:
Page 553 and 554:
Page 555 and 556:
Page 557 and 558:
Page 559 and 560:
Page 561 and 562:
Page 563 and 564:
Page 565 and 566:
Page 567 and 568:
Page 569 and 570:
Page 571 and 572:
Page 573 and 574:
Page 575 and 576:
Page 577 and 578:
Page 579 and 580:
Page 581 and 582:
Page 583 and 584:
Section 12 Data Transfer Controller
Page 585 and 586:
Page 587 and 588:
Page 589 and 590:
Page 591 and 592:
Page 593 and 594:
Page 595 and 596:
Page 597 and 598:
Page 599 and 600:
Page 601 and 602:
Page 603 and 604:
Page 605 and 606:
Page 607 and 608:
Page 609 and 610:
Page 611 and 612:
Page 613 and 614:
Page 615 and 616:
Page 617 and 618:
Page 619 and 620:
Page 621 and 622:
Section 13 I/O Ports Section 13 I/O
Page 623 and 624:
Section 13 I/O Ports Function Port
Page 625 and 626:
Page 627 and 628:
Page 629 and 630:
Section 13 I/O Ports 13.1 Register
Page 631 and 632:
Section 13 I/O Ports 13.1.2 Data Re
Page 633 and 634:
Section 13 I/O Ports 13.1.5 Pull-Up
Page 635 and 636:
Section 13 I/O Ports 13.2 Output Bu
Page 637 and 638:
Section 13 I/O Ports (4) P14/DREQ1-
Page 639 and 640:
Section 13 I/O Ports (8) P10/DREQ0-
Page 641 and 642:
Section 13 I/O Ports (4) P24/PO4/TI
Page 643 and 644:
Page 645 and 646:
Section 13 I/O Ports (4) P34/PO12/T
Page 647 and 648:
Page 649 and 650:
Section 13 I/O Ports (3) P63/TMRI3/
Page 651 and 652:
Section 13 I/O Ports 13.2.6 Port A
Page 653 and 654:
Section 13 I/O Ports (5) PA3/LLWR/L
Page 655 and 656:
Section 13 I/O Ports 13.2.7 Port B
Page 657 and 658:
Section 13 I/O Ports (5) PB3/CS3/CS
Page 659 and 660:
Section 13 I/O Ports 13.2.8 Port C
Page 661 and 662:
Section 13 I/O Ports (1) PE7/A15, P
Page 663 and 664:
Section 13 I/O Ports (4) PF4/A20 Th
Page 665 and 666:
Section 13 I/O Ports (8) PF0/A16 Th
Page 667 and 668:
Section 13 I/O Ports 13.2.14 Port J
Page 669 and 670:
Section 13 I/O Ports (5) PJ3 The pi
Page 671 and 672:
Section 13 I/O Ports 13.2.15 Port K
Page 673 and 674:
Section 13 I/O Ports (5) PK3 The pi
Page 675 and 676:
Section 13 I/O Ports 13.2.16 Port M
Page 677 and 678:
Section 13 I/O Ports Table 13.5 Ava
Page 679 and 680:
Section 13 I/O Ports Port P2 0 P3 7
Page 681 and 682:
Section 13 I/O Ports Port Output Sp
Page 683 and 684:
Section 13 I/O Ports Port PB PC PD
Page 685 and 686:
Section 13 I/O Ports Port PI PM Out
Page 687 and 688:
Section 13 I/O Ports Bit Bit Name I
Page 689 and 690:
Page 691 and 692:
Page 693 and 694:
Section 13 I/O Ports 13.3.6 Port Fu
Page 695 and 696:
Page 697 and 698:
Page 699 and 700:
Section 13 I/O Ports 13.3.10 Port F
Page 701 and 702:
Section 13 I/O Ports 13.4 Usage Not
Page 703 and 704:
Section 14 16-Bit Timer Pulse Unit
Page 705 and 706:
Page 707 and 708:
Page 709 and 710:
Page 711 and 712:
Page 713 and 714:
Page 715 and 716:
Page 717 and 718:
Page 719 and 720:
Page 721 and 722:
Page 723 and 724:
Page 725 and 726:
Page 727 and 728:
Page 729 and 730:
Page 731 and 732:
Page 733 and 734:
Page 735 and 736:
Page 737 and 738:
Page 739 and 740:
Page 741 and 742:
Page 743 and 744:
Page 745 and 746:
Page 747 and 748:
Page 749 and 750:
Page 751 and 752:
Page 753 and 754:
Page 755 and 756:
Page 757 and 758:
Page 759 and 760:
Page 761 and 762:
Page 763 and 764:
Page 765 and 766:
Page 767 and 768:
Page 769 and 770:
Page 771 and 772:
Page 773 and 774:
Page 775 and 776:
Page 777 and 778:
Page 779 and 780:
Page 781 and 782:
Page 783 and 784:
Page 785 and 786:
Page 787 and 788:
Page 789 and 790:
Section 15 Programmable Pulse Gener
Page 791 and 792:
Page 793 and 794:
Page 795 and 796:
Page 797 and 798:
Page 799 and 800:
Page 801 and 802:
Page 803 and 804:
Page 805 and 806:
Page 807 and 808:
Page 809 and 810:
Page 811 and 812:
Page 813 and 814:
Section 16 8-Bit Timers (TMR) Secti
Page 815 and 816:
Section 16 8-Bit Timers (TMR) Inter
Page 817 and 818:
Section 16 8-Bit Timers (TMR) Clock
Page 819 and 820:
Section 16 8-Bit Timers (TMR) 16.3
Page 821 and 822:
Section 16 8-Bit Timers (TMR) 16.3.
Page 823 and 824:
Section 16 8-Bit Timers (TMR) Bit B
Page 825 and 826:
Section 16 8-Bit Timers (TMR) Table
Page 827 and 828:
Section 16 8-Bit Timers (TMR) Table
Page 829 and 830:
Page 831 and 832:
Section 16 8-Bit Timers (TMR) Bit 1
Page 833 and 834:
Section 16 8-Bit Timers (TMR) Bit 1
Page 835 and 836:
Page 837 and 838:
Page 839 and 840:
Section 16 8-Bit Timers (TMR) Pφ E
Page 841 and 842:
Page 843 and 844:
Page 845 and 846:
Page 847 and 848:
Page 849 and 850:
Section 17 32K Timer (TM32K) Sectio
Page 851 and 852:
Section 17 32K Timer (TM32K) Bit Bi
Page 853 and 854:
Section 17 32K Timer (TM32K) 17.3 O
Page 855 and 856:
Section 17 32K Timer (TM32K) To ave
Page 857 and 858:
Section 17 32K Timer (TM32K) 17.5 U
Page 859 and 860:
Section 18 Watchdog Timer (WDT) Sec
Page 861 and 862:
Section 18 Watchdog Timer (WDT) 18.
Page 863 and 864:
Page 865 and 866:
Section 18 Watchdog Timer (WDT) H'F
Page 867 and 868:
Page 869 and 870:
Page 871 and 872:
Section 19 Serial Communication Int
Page 873 and 874:
Page 875 and 876:
Page 877 and 878:
Page 879 and 880:
Page 881 and 882:
Page 883 and 884:
Page 885 and 886:
Page 887 and 888:
Page 889 and 890:
Page 891 and 892:
Page 893 and 894:
Page 895 and 896:
Page 897 and 898:
Page 899 and 900:
Page 901 and 902:
Page 903 and 904:
Page 905 and 906:
Page 907 and 908:
Page 909 and 910:
Page 911 and 912:
Page 913 and 914:
Page 915 and 916:
Page 917 and 918:
Page 919 and 920:
Page 921 and 922:
Page 923 and 924:
Page 925 and 926:
Page 927 and 928:
Page 929 and 930:
Page 931 and 932:
Page 933 and 934:
Page 935 and 936:
Page 937 and 938:
Page 939 and 940:
Page 941 and 942:
Page 943 and 944:
Page 945 and 946:
Page 947 and 948:
Page 949 and 950:
Page 951 and 952:
Page 953 and 954:
Page 955 and 956:
Page 957 and 958:
Page 959 and 960:
Page 961 and 962:
Page 963 and 964:
Section 20 USB Function Module (USB
Page 965 and 966:
Page 967 and 968:
Page 969 and 970:
Page 971 and 972:
Page 973 and 974:
Page 975 and 976:
Page 977 and 978:
Page 979 and 980:
Page 981 and 982:
Page 983 and 984:
Page 985 and 986:
Page 987 and 988:
Page 989 and 990:
Page 991 and 992:
Page 993 and 994:
Page 995 and 996:
Page 997 and 998:
Page 999 and 1000:
Page 1001 and 1002:
Page 1003 and 1004:
Page 1005 and 1006:
Page 1007 and 1008:
Page 1009 and 1010:
Page 1011 and 1012:
Page 1013 and 1014:
Page 1015 and 1016:
Page 1017 and 1018:
Page 1019 and 1020:
Page 1021 and 1022:
Page 1023 and 1024:
Page 1025 and 1026:
Page 1027 and 1028:
Page 1029 and 1030:
Section 21 I 2 C Bus Interface 2 (I
Page 1031 and 1032:
Page 1033 and 1034:
Page 1035 and 1036:
Page 1037 and 1038:
Page 1039 and 1040:
Page 1041 and 1042:
Page 1043 and 1044:
Page 1045 and 1046:
Page 1047 and 1048:
Page 1049 and 1050:
Page 1051 and 1052:
Page 1053 and 1054:
Page 1055 and 1056:
Page 1057 and 1058:
Page 1059 and 1060:
Page 1061 and 1062:
Page 1063 and 1064:
Section 22 A/D Converter Section 22
Page 1065 and 1066:
Section 22 A/D Converter Module dat
Page 1067 and 1068:
Section 22 A/D Converter 22.3 Regis
Page 1069 and 1070:
Section 22 A/D Converter 22.3.2 A/D
Page 1071 and 1072:
Section 22 A/D Converter Bit 3 2 1
Page 1073 and 1074:
Section 22 A/D Converter Bit Bit Na
Page 1075 and 1076:
Page 1077 and 1078:
Page 1079 and 1080:
Page 1081 and 1082:
Page 1083 and 1084:
Section 22 A/D Converter Set* ADIE
Page 1085 and 1086:
Section 22 A/D Converter A/D conver
Page 1087 and 1088:
Section 22 A/D Converter 22.4.3 Inp
Page 1089 and 1090:
Section 22 A/D Converter Table 22.3
Page 1091 and 1092:
Page 1093 and 1094:
Section 22 A/D Converter Pφ ADTRG0
Page 1095 and 1096:
Section 22 A/D Converter 22.6 A/D C
Page 1097 and 1098:
Section 22 A/D Converter 22.7 Usage
Page 1099 and 1100:
Section 22 A/D Converter Start Exte
Page 1101 and 1102:
Section 22 A/D Converter 22.7.6 Inf
Page 1103 and 1104:
Page 1105 and 1106:
Section 23 D/A Converter Section 23
Page 1107 and 1108:
Section 23 D/A Converter 23.3.1 D/A
Page 1109 and 1110:
Section 23 D/A Converter 23.3.5 D/A
Page 1111 and 1112:
Section 23 D/A Converter 23.4 Opera
Page 1113 and 1114:
Section 23 D/A Converter 23.5 Usage
Page 1115 and 1116:
Section 24 RAM Section 24 RAM This
Page 1117 and 1118:
Section 25 Flash Memory Section 25
Page 1119 and 1120:
Section 25 Flash Memory 25.2 Mode T
Page 1121 and 1122:
Section 25 Flash Memory 25.3 Memory
Page 1123 and 1124:
Section 25 Flash Memory 25.5 Progra
Page 1125 and 1126:
Section 25 Flash Memory 25.6 Input/
Page 1127 and 1128:
Section 25 Flash Memory Table 25.3
Page 1129 and 1130:
Section 25 Flash Memory Bit Bit Nam
Page 1131 and 1132:
Section 25 Flash Memory (2) Flash P
Page 1133 and 1134:
Section 25 Flash Memory (5) Flash M
Page 1135 and 1136:
Section 25 Flash Memory 25.7.2 Prog
Page 1137 and 1138:
Section 25 Flash Memory (2) Downloa
Page 1139 and 1140:
Section 25 Flash Memory (b) Program
Page 1141 and 1142:
Section 25 Flash Memory (c) Erasure
Page 1143 and 1144:
Section 25 Flash Memory Bit Bit Nam
Page 1145 and 1146:
Section 25 Flash Memory (6) Flash M
Page 1147 and 1148:
Section 25 Flash Memory 25.7.3 RAM
Page 1149 and 1150:
Section 25 Flash Memory 25.8.1 Boot
Page 1151 and 1152:
Section 25 Flash Memory (2) State T
Page 1153 and 1154:
Section 25 Flash Memory 25.8.2 USB
Page 1155 and 1156:
Section 25 Flash Memory (2) State T
Page 1157 and 1158:
Section 25 Flash Memory 25.8.3 User
Page 1159 and 1160:
Section 25 Flash Memory (2) Program
Page 1161 and 1162:
Section 25 Flash Memory ⎯ The ret
Page 1163 and 1164:
Section 25 Flash Memory ⎯ Example
Page 1165 and 1166:
Section 25 Flash Memory The procedu
Page 1167 and 1168:
Section 25 Flash Memory In figure 2
Page 1169 and 1170:
Section 25 Flash Memory In user boo
Page 1171 and 1172:
Section 25 Flash Memory Memory MAT
Page 1173 and 1174:
Page 1175 and 1176:
Page 1177 and 1178:
Section 25 Flash Memory 25.9 Protec
Page 1179 and 1180:
Section 25 Flash Memory Error prote
Page 1181 and 1182:
Section 25 Flash Memory Figure 25.2
Page 1183 and 1184:
Section 25 Flash Memory 25.11 Switc
Page 1185 and 1186:
Section 25 Flash Memory 3. Programm
Page 1187 and 1188:
Section 25 Flash Memory 5. Memory r
Page 1189 and 1190:
Section 25 Flash Memory The selecti
Page 1191 and 1192:
Section 25 Flash Memory (d) Clock M
Page 1193 and 1194:
Section 25 Flash Memory (f) Operati
Page 1195 and 1196:
Section 25 Flash Memory • Area-la
Page 1197 and 1198:
Section 25 Flash Memory Error Respo
Page 1199 and 1200:
Section 25 Flash Memory (5) Transit
Page 1201 and 1202:
Section 25 Flash Memory (8) Program
Page 1203 and 1204:
Section 25 Flash Memory • Erasure
Page 1205 and 1206:
Section 25 Flash Memory (c) 128-Byt
Page 1207 and 1208:
Section 25 Flash Memory (e) Block E
Page 1209 and 1210:
Section 25 Flash Memory (g) User Bo
Page 1211 and 1212:
Section 25 Flash Memory (k) Boot Pr
Page 1213 and 1214:
Section 25 Flash Memory 25.14 Usage
Page 1215 and 1216:
Section 26 Boundary Scan Section 26
Page 1217 and 1218:
Section 26 Boundary Scan 26.4 Regis
Page 1219 and 1220:
Section 26 Boundary Scan Table 26.3
Page 1221 and 1222:
Section 26 Boundary Scan Pin No Pin
Page 1223 and 1224:
Section 26 Boundary Scan Pin No Pin
Page 1225 and 1226:
Section 26 Boundary Scan 26.4.4 IDC
Page 1227 and 1228:
Section 26 Boundary Scan 26.5.2 Com
Page 1229 and 1230:
Section 26 Boundary Scan 26.6 Usage
Page 1231 and 1232:
Section 27 Clock Pulse Generator Se
Page 1233 and 1234:
Section 27 Clock Pulse Generator 27
Page 1235 and 1236:
Section 27 Clock Pulse Generator Bi
Page 1237 and 1238:
Page 1239 and 1240:
Page 1241 and 1242:
Page 1243 and 1244:
Section 27 Clock Pulse Generator Fi
Page 1245 and 1246:
Section 28 Power-Down Modes Section
Page 1247 and 1248:
Section 28 Power-Down Modes Notes:
Page 1249 and 1250:
Section 28 Power-Down Modes 28.2 Re
Page 1251 and 1252:
Section 28 Power-Down Modes Bit Bit
Page 1253 and 1254:
Section 28 Power-Down Modes • MST
Page 1255 and 1256:
Section 28 Power-Down Modes • MST
Page 1257 and 1258:
Section 28 Power-Down Modes Bit 7 6
Page 1259 and 1260:
Page 1261 and 1262:
Section 28 Power-Down Modes 28.2.6
Page 1263 and 1264:
Page 1265 and 1266:
Page 1267 and 1268:
Page 1269 and 1270:
Section 28 Power-Down Modes 28.3 Mu
Page 1271 and 1272:
Section 28 Power-Down Modes 28.5 Sl
Page 1273 and 1274:
Section 28 Power-Down Modes 28.7 So
Page 1275 and 1276:
Page 1277 and 1278:
Section 28 Power-Down Modes 28.8 De
Page 1279 and 1280:
Section 28 Power-Down Modes 4. Exit
Page 1281 and 1282:
Page 1283 and 1284:
Section 28 Power-Down Modes Oscilla
Page 1285 and 1286:
Section 28 Power-Down Modes (3) Dee
Page 1287 and 1288:
Section 28 Power-Down Modes Clear a
Page 1289 and 1290:
Page 1291 and 1292:
Section 28 Power-Down Modes SLPIE =
Page 1294 and 1295:
Section 28 Power-Down Modes 28.12 U
Page 1296 and 1297:
Section 28 Power-Down Modes Rev. 1.
Page 1298 and 1299:
Section 29 List of Registers 29.1 R
Page 1300 and 1301:
Section 29 List of Registers Access
Page 1302 and 1303:
Page 1304 and 1305:
Page 1306 and 1307:
Page 1308 and 1309:
Page 1310 and 1311:
Page 1312 and 1313:
Page 1314 and 1315:
Section 29 List of Registers 29.2 R
Page 1316 and 1317:
Section 29 List of Registers Regist
Page 1318 and 1319:
Page 1320 and 1321:
Page 1322 and 1323:
Page 1324 and 1325:
Page 1326 and 1327:
Page 1328 and 1329:
Page 1330 and 1331:
Page 1332 and 1333:
Page 1334 and 1335:
Page 1336 and 1337:
Page 1338 and 1339:
Page 1340 and 1341:
Section 29 List of Registers Notes:
Page 1342 and 1343:
Page 1344 and 1345:
Page 1346 and 1347:
Page 1348 and 1349:
Page 1350 and 1351:
Page 1352 and 1353:
Page 1354 and 1355:
Page 1356 and 1357:
Page 1358 and 1359:
Section 29 List of Registers Rev. 1
Page 1360 and 1361:
Section 30 Electrical Characteristi
Page 1362 and 1363:
Page 1364 and 1365:
Page 1366 and 1367:
Page 1368 and 1369:
Page 1370 and 1371:
Page 1372 and 1373:
Page 1374 and 1375:
Page 1376 and 1377:
Page 1378 and 1379:
Page 1380 and 1381:
Page 1382 and 1383:
Page 1384 and 1385:
Page 1386 and 1387:
t WDD t WDS2 t WDH3 Section 30 Elec
Page 1388 and 1389:
Page 1390 and 1391:
Page 1392 and 1393:
Page 1394 and 1395:
Page 1396 and 1397:
Page 1398 and 1399:
Page 1400 and 1401:
Page 1402 and 1403:
Page 1404 and 1405:
Page 1406 and 1407:
Page 1408 and 1409:
Page 1410 and 1411:
Page 1412 and 1413:
Page 1414 and 1415:
Page 1416 and 1417:
Page 1418 and 1419:
Appendix Port Name PA2/ BREQ/ WAIT
Page 1420 and 1421:
Appendix Port Name PB6/ CS6-D/ (RD/
Page 1422 and 1423:
Appendix B. Product Lineup Product
Page 1424 and 1425:
Appendix D. Treatment of Unused Pin
Page 1426 and 1427:
Appendix Rev. 1.00 Jan. 29, 2010 Pa
Page 1428 and 1429:
Cluster transfer modes.............
Page 1430 and 1431:
P Package dimensions...............
Page 1432 and 1433:
PODRH .............................
Page 1434 and 1435:
Rev. 1.00 Jan. 29, 2010 Page 1402 o
Page 1436:
Sales Strategic Planning Div. Nippo
show all

H8SX/1665MZ Group Hardware Manual - Renesas Electronics

Create successful ePaper yourself

Delete template?

Save as template?