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OCTOBER 2010 issue n°100 THE DISRUPTIVE SEMICONDUCTOR TECHNOLOGIES MAGAZINE All over the World, stay connected Our readers, your business... Copyrights © Yole Développement SA. All rights reserved - Recycled paper Become a sponsor today! In-depth Market & Technology Analysis Quarterly Magazines Combined reach to over 15,000 subscribers Contact: Editorial, Advertising & Subscriptions leroy@yole.fr / www.i-micronews.com Y O L E D É V E L O P P E M E N T 18
OCTOBER 2010 issue n°100 THE DISRUPTIVE SEMICONDUCTOR TECHNOLOGIES MAGAZINE ADVANCED PACKAGING 3D-IC memory with wide I/O interface is coming by 2013 says NOKIA From page 1 Kauppi Kujala focused particularly on the “wide IO interface” concept, which aims at increasing the bandwidth between the memory and its driving logic IC thanks to a large “high IO count” data bus between the two circuits. M. Kujala announced that Nokia is planning to integrate wide IO interface structures using TSVs for mobile phones in volumes starting in 2013. These integrated solutions will first be driven in high end phones addressing the need for higher bandwidth between the application processor and its DRAMs and for lower power consumption too. Nokia’s preference and first target is to integrate a stack of 4 DRAMs with TSVs on a processor with TSVs, all in a single package. www.yole.fr Wide IO Package Solutions • Single package Wide IO. Logic + up to 4 DRAM. F2B connection. • Wide IO ogic + 1 DRAM & additional DRAM on bord. F2B connection, no TSV needed for memory. • Wide IO POP with Logic + 1 DRAM in bottom package & additional memory as POP F2B connection, no TSV needed for memory. The Wide I/O interface concept to interconnect Logic and stacked DRAM was recently discussed by NOKIA Qualcomm defines format for 3-D chip stress Qualcomm has teamed up with Synopsys to define a new data exchange format it believes could be critical for supporting 3-D chip stacks that use through silicon vias. Qualcomm has already gotten support from at least one foundry and one chip assembler for the so-called Stress Exchange Format. The new technique is one of many efforts driving 3-D chip stacks using through silicon vias (TSVs). The Global Semiconductor Alliance announced it is forming a working group on TSVs. Nokia said it has TSVs on its road map at a recent Sematech meeting in Taiwan. And Jedec is defining a standard for memory chips using TSVs. Digital cameras already use TSVs with 30-50 micron spacing to stack CMOS imagers, memories and DSPs. A range of other applications are in the labs using TSVs with spacings in the single digits, said Nakamoto. "You will see products in the market next year," he said. SEF is essentially a way existing global an local packaging models can share stress data with new local models for chips using TSVs. The 3-D stacks face stress from a variety of mechanical and thermal sources, in part because the stacked dice and vias are sometimes made of different materials. SEF calculates an overall factor called residual stress based on the result of a variety of stress factors. It applies a 3-D matrix to the silicon area and defi nes residual strain vectors for each sector. The approach requires foundries to supply chip designers with 3-D Process Design Kits that provide data about the materials they use. Synopsys has become the fi rst EDA company to automate the process of porting SEF data into a tool, in this case its Fammos technical CAD program. Qualcomm has created multiple proof-of-concept designs using SEF including some fabricated chips about which it would not share details. Ultimately, Qualcomm hopes all foundries, packaging houses and EDA vendors will support SEF. www.qualcomm.com RUSNANO to open new 3D Assembly R&D center in Russia A project to establish technology center for three-dimensional assembly of integrated circuits in Russia has secured approval from the Supervisory Council of RUSNANO. The technology for three-dimensional assembly of semiconductor elements, or 3D assembly, is one of today’s most promising methods for reducing the size of the integrated circuit. It does this by making the substrate more dense, by raising the connectivity inside the chip, and by reducing its energy consumption. The technology makes it possible to combine components—digital and analog circuits, memory, and MEMS systems—that have been produced with different technologies in one encasement. The 3D assembly raises the reliability of microelectronic goods and continues the downward trend in production costs. In 2008 the world market for 3D assembly was $1.3 billion. Experts forecast that microelectronic products manufactured with 3D assembly will grow fi vefold by 2012 after which the technology will attain widespread use. Forecasted volume in 2015 is $42 billion. The project that RUSNANO has agreed to support will create a center where technological processes for 3D assembly will be developed. There the project company will organize production of three lines: electrochemical materials based on self-optimizing additives used in 3D assembly of chips with silicon current-conducting channels, metallization of integrated circuits, and solar elements. In addition, the project intends to produce electronic elements for 3D assembly that are formed from its own electrochemical materials. In 2015 sales of the project company in the 3D assembly sector are forecasted at 992 million rubles in the global market and 1.13 billion rubles in the domestic market. In the sector for electrochemical materials for copper metallization, something not done in Russia to date, the company will achieve 6.7 percent of the world market and 100 percent of the Russian market. Project company earnings in 2015 are put at 2.5 billion rubles. New production will be based on the unique experience of the project applicants, Voronezh Semiconductor Plant–Assembly and NANO3D SYSTEMS LLC. There will be two phases for realization of the project: In the fi rst (2010–2012), the company will organize production of electrochemical materials and establish pilot production of electronic devices using 3D assembly. In the second phase (2013–2015), production of electrochemical materials will grow and commercial production of electronic devices will begin. The total budget for project implementation is about $50Million. RUSNANO will invest up to $10M in equity of the project company and, in the second phase, extend a guarantee of up to $20M. www.rusnano.com Copyrights © Yole Développement SA. All rights reserved - Recycled paper 19
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