Embedded Die - I-Micronews
Embedded Die - I-Micronews
Embedded Die - I-Micronews
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<strong>Embedded</strong> Wafer-Level-Package technologies<br />
Fan-out WLP<br />
• Wafers or panels are<br />
(re)configured<br />
FO-WLP<br />
– By placing known good ICs active<br />
face down on a foil and by overmolding<br />
them<br />
– These wafers/panels are then<br />
flipped and processed back in the<br />
wafer fab with RDL, bumping, …<br />
<strong>Embedded</strong><br />
IC in PCB<br />
Chip embedding<br />
(or embedded IC in PCB)<br />
• Known good ICs and picked<br />
– and placed on top of an organic<br />
layer of Printed circuit board<br />
– Subsequent layers are laminated<br />
on top and regular PCB<br />
manufacturing operations take<br />
place on the panel with the<br />
embedded ICs<br />
© 2010 • 15<br />
Both these technologies are considered (n+1) technologies versus<br />
WLCSP. Among others, they offer the following differential benefits:<br />
fan-out area for larger IO densities than WLCSP<br />
Collective wafer level processing of known good dice (KGD)<br />
Higher expected second level reliability (package connection to the<br />
mother board)<br />
Back-side protection<br />
System-in-package and 3D integration capabilities<br />
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