May 2013 - I-Micronews

3D
ISSUE N°27
MAY 2013
Packaging
Magazine on 3DIC, TSV, WLP & Embedded Die Technologies
Taiwan:
Leading
location
for flip chip
bumping
Printed on recycled paper
Industry review
Could copper
pillar change
the ecosystem?
A CLOSER LOOK
Will CPB be the next
evolution of FC?
analyst corner
Mainstream
flip chip bumping
starts to move
to copper pillars
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technologies?
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• A new top-down approach, leading to an exhaustive
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• Micro-bumping and accurate modeling of memory
and HB-LED applications
• Market data for TIM, underfills, substrates and
Flip-Chip bonders
• Detailed technology roadmap
Flip Chip
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M A Y 2 0 1 3 I S S U E N ° 2 7
E D I T O R I A L
An established platform rescues most
advanced silicon technologies
Dear 3D Packaging readers,
It’s my pleasure to share with you our outlook for the fantastic, long-lasting
potential of a proven Advanced Packaging technology: flip chip.
No doubt you’re wondering why the spotlight is now being shone on this
long-established technology. There are several reasons, two of which are
value and technology. Technology equates to the customer’s perception
of a product’s advantages, be they features, performance or reliability.
Of the three, performance has always been the key decision-making
parameter for consumers, because each new device generation brings
significant speed improvements like calculation, graphical display or data
transfer time. Performance improvement is the outcome of mainstream
semiconductor technology’s node change, and it always carries large
...the opening of
interconnection between
heterogeneous
chips in the same package,
flip chip is the ideal path...
investments. Of course, return on investment is the driving force for
most IC manufacturers -- but going from a 90nm technology node to 32
and beyond requires an increased interconnect need that wire-bonding
simply cannot match. So what could be the way out?
Enter flip chip, which has resurfaced to rescue designers and solve the
technological challenge of linking the sub-20 nanometer gate length to
the millimeter world. With copper pillar pitch reduction allowing for wider
I/O connectivity, and the opening of interconnection between heterogeneous
chips in the same package, flip chip is the ideal path. Moreover,
any Advanced Packaging scheme ends with bumping opening the
door to very large adoption.
Regarding value, flip chip offers the outstanding benefit of being realized
at wafer level, thus significantly reducing manufacturing cost compared
e v e n t s
• Electronic Components and Technology
Conference (ECTC)
May 28 to 31, 2013 - Las Vegas, NV
• SEMICON Russia
June 5 to 6, 2013 - Moscow, Russia
• SEMI Networking Day: Packaging - Key
Driver for System Integration
June 27, 2013 - Porto, Portugal
to single chip wire bonding.
I’m confident that by the end of this 3D Packaging issue, you’ll have a
much better understanding of Flip chip’s technology, market and potential.
Christophe Fitamant
Sales & Marketing Director
Yole Développement
fitamant@yole.fr
• SEMICON West
July 9 to 11, 2013 - San Francisco, CA
platinum partners:
3 D P a c k a g i n g 3
For more information, please contact S. Leroy (leroy@yole.fr)

M A Y 2 0 1 3 I S S U E N ° 2 7
C O N T E N T S
INDUSTRY REVIEW
• Could copper pillar change the ecosystem? 6
YOLE ASKS
• Keeping up with the industry heavyweights 10
A CLOSER LOOK
• Will CPB be the next evolution of FC? 12
(Courtesy of FlipChip
International)
• The evolution of Flip Chip packaging 14
Analyst Corner
• Mainstream flip chip bumping starts to move to copper pillars 16
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Watch it now
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2013 PROGRAM:
June 11
Silicon Microfluidics:
Myth or Reality?
July 9
IR imagers:
How cost decrease
will generate
new markets
Flip Chip: An established
platform still in mutation...
...And despite its longevity, Flip Chip is still able to
serve the most advanced packaging technologies
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M A Y 2 0 1 3 I S S U E N ° 2 7
INDUSTRY REVIEW
Three quarter wafer
Cu pillar bumps
(Courtesy of
Amkor Technology)
Could copper pillar change
the ecosystem?
The future of bumping is copper, and that could change everything. Though originally
developed at the IDMs, players from foundries to OSATs are now developing a variety
of differing copper pillar and micro-bumping solutions for a range of customers,
looking re-designing the substrate, weighing extending reflow vs scaling thermal
compression bonding, and developing probe and test systems.
Though copper bumping has been around for
years, higher density devices mean growing
demand for higher density interconnect
than the ~130-140µm pitch that can be done with
solder bumps. As mobile application or baseband
processors increasingly require the high density of
copper pillars for small size at 28nm and below, and
memory soon starts to go to wide I/O and DDR4
stacked with processors needing higher pin counts
and reduced parasitics, manufacturers are focusing
on scaling copper technology to tighter pitches,
higher volumes, and of course lower costs.
“For copper pillar bumping, the industry will have
to solve similar challenges as it did for copper wire
bonding—the materials are different, the substrates
are different, and the designs are different. Moving
beyond solder will require a whole new ecosystem,
and will require working closely with our customers
and with our materials and equipment partners,”
says Bill Chen, ASE Fellow and Senior Technical
Advisor.
“Copper is a node change for bumping,” concurs David
McCann, VP of Packaging R&D at GLOBALFOUNDRIES,
pointing out that this node should be extendible more
than the usual 7 years, all the way down through
10µm pitch connections and below. “We see copper as
a core competency for several generations,” he adds,
noting that the company is investing significantly in
people and projects to develop copper expertise,
counting on the same core knowledge and tools to
extend to beyond copper pillar and micro-bumping
down to copper-to-copper bumpless bonding below
14µm. GLOBALFOUNDRIES is developing Cu pillar
technology in its Dresden facility and will be adding
a bump facility, focusing on Cu pillar production at
its Fab 8 facility in New York. The New York facility
will enable interconnect and package R&D co-located
with its front-end development teams for advanced
nodes. Development in Dresden focuses on 100-
110µm pitch bumps for 28nm, and 40µm/80µm
pitch for 20nm.
STATS ChipPAC is currently doing staggered
40µm/80µm pitch Cu columns, with 20-30µm bumps
on 80µm pitch centers for 28nm mobile processors,
reports Raj Pendse, VP and Chief Marketing Officer.
Similar technology should be extendible to 20nm
processors, he suggests, as the relatively low I/O
density of the power and ground in the center of
the processor die means there will likely be enough
room to just add more rows of the same 80µm pitch
columns.
6
3 D P a c k a g i n g

I S S U E N ° 2 7
M A Y 2 0 1 3
a
Foundries are also developing their own
solutions with their customers. “Some
foundries want to control the entire supply
chain but we want to enable our customers’
supply chain choices. We also need the fast
feedback of probe results to the fab drive
early yields,” says McCann. “But we don’t
Pendse concurs that OSATs will take a larger
role as the technology matures, as dividing
responsibility for yield between the fab and
OSAT when transferring bumped wafers will
become easier as bumping reaches consistently
high yields, and can be more easily handled
by agreements on expected performance.
“At 20-14nm, it’s not clear what kind of pitch will be
required,” says Dr Raj Pendse, STATS ChipPAC.
b
fcCuBE interconnect of 80um/40um pitch TV
using (a) Mass Reflow (MR) and (b)
Thermo-Compression Bonding (TCB) processes
(Courtesy of STATS ChipPAC)
More players, more approaches
Copper pillar bumping means a new era for the
OSATs, says Chen, noting that the earlier solder
bumping technologies were developed at the
IDMs like IBM and Intel, and the OSATs’ job was
simply to do just what the IDMs had done. But
this time the OSATs are developing their own
versions of the technology with their customers.
“This generation of copper pillar that started
with TI follows a general pattern of laying down
an under-bump metallization layer, then plating
over it and using some kind of photo resist, but
after that there is plenty of room for people to
do things differently,” he notes.
want to do production packaging. We want to
drive our logic sales, and we want to enable
the OSATs’ business.” While the leading edge
work at future nodes will likely start at the
foundry, high volume readiness will be verified
at the OSAT, and bump and probe will move
to the OSATs for mature nodes and devices.
The need for co-development of BEOL stacks,
interconnect and assembly will necessitate
close collaboration on assembly. At future
nodes, however, interconnect and packaging
processes that happen at the wafer level
will require more fab-like processes and
investment in traditional CVD, PVD, and CMP
fab tools. “Both foundry and OSAT will likely
support middle-of-the-line processing, and
there may be a merging of business models in
the future,” he suggests.
Foundries may also revisit if the lower-margin
bumping business makes sense for them as
the technology matures. And the chip stacking
technology may eventually move away from the
front-end fabs’ area of expertise, if it moves away
from using silicon wafers for re-distribution or
interposer substrates and instead finds ways to
use the lower cost LCD infrastructure for fan-out
WLP, or to use panel or glass 2.5D interposers.
Bringing down costs by re-thinking
substrate design
Plenty of technical issues remain, however, to
move copper pillar and micro-bumping to high
volume production at smaller geometries and
lower costs. Finding ways to reduce the costs
of the denser and denser substrates is one key
path.
Bumping interconnect technology roadmap for FC BGA
(Flip Chip report, Yole Développement, March 2013)
Pitch (µm)
160
140
120
100
80
60
Screen printing
45 nm
Electroplating
Solder bump
conductive polymer bump
Electroplating / Evaporation / Stud bumping
Au bump
Solder bump
Cu-pillars
Micro-bump
bonding
Bump-less
‘pads’?
40
Cu-Pillars
µ-Bumps
20
32 nm
22 nm
18 nm
0
2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
Flip chip
array
Flip chip
peripheral
Eutectic, High Lead, Pb free
(SnAgCu)
Lead free, Au stud, Solder bump, Cu pillars
3 D P a c k a g i n g
7

M A Y 2 0 1 3 I S S U E N ° 2 7
Copper pillar bump
(Courtesy of GLOBALFOUNDRIES)
“Thermo
compression
bonding has still
had very limited
use in high volume
production,”
says Bill Chen, ASE.
Moving from bond pads to the finer traces of the
bond-on-lead approach has helped bring down
costs initially by allowing more efficient routing, to
reduce the number of layers required to reduce the
significant cost of the substrate. Pendse notes that
this may eliminate the need for the solder mask
for solder confinement, and the associated tight
tolerances on solder mask alignment. The use of
copper column bumps, with the greater stand-off
heights achievable, also makes it easier to use mold
instead of capillary underfill.
Re-thinking substrate design will continue to be the
main path to bring down costs, argues Chen.“The idea
of a pillar gives us the opportunity to significantly rethink
what flip chip means, and allows us to re-think
everything we’re doing to design solutions for each
application. It gives the design a lot of freedom.” He
notes that by working closely with chip designers
the copper pillar substrate can be simplified from
expensive build up board down to lower cost four
layer or all subtractive substrates.
Or perhaps the industry may need to re-think the
entire approach of routing and attaching ever
denser die I/Os on ever denser multilayer substrates.
Pendse suggests that at some point this no longer
makes sense, since new generations of die quickly
come down in cost, but the substrate and packaging
costs remain high even in maturity. “At 20µm/40µm
you start to pay a really high premium [for the high
density substrate],” he notes. “We need to move
to a new technology to get around this. We think
it will be fan-out wafer level packaging, which can
give a 2X jump in density.” He suggests moving
to more scalable chip-like solutions for the routing
could be a cheaper alternative at some point.
Instead of attaching the die to a ready-made
substrate, the packaging house would redistribute
the dies across a 300mm silicon wafer, then build
thin film redistribution layers of metal and dielectric
on top to carry the signal from the die pad to the
BGA pad, an approach that could potentially make
10µm traces at lower cost. “For these sorts of I/O
densities we can’t afford to be pushing the leading
edge of substrate technology. We should move to a
different technology that’s more in the sweet spot for
the required geometries,” he argues. Though FOWLP
is in high volume production now using wafer-like
carriers, it could be scaled several fold by changing
the carrier format. “We’re now using 300mm wafers
as the carriers, but we don’t need to use the silicon
infrastructure for 10µm lines,” he notes. “We could
use large area substrates like 2G LCD panels and
tools from the LCD industry.”
Reflow or thermal compression
bonding?
Finding ways to extend the use of mass reflow
attachment to tighter pitch copper bumps could also
help hold down costs, perhaps putting off the need
to convert to more expensive thermal compression
bonding. Bond-on-lead interconnection allows
reflow on current products, but finer pitches may
eventually push the industry to thermal compression
bonding, as reflow placement and accuracy may not
be sufficient. “At 20-14nm, it’s not clear what kind
of pitch will be required,” says Pendse, suggesting
that 14nm devices might need 30µm/60µm pitch
bumping with 15µm lines and spaces for escape
routing in 2-3 years, which could be still doable with
reflow, or might need thermal compression bonding.
But thermal compression bonding will likely be
needed for 2.5D/3D applications at

ANNONCE 905 273:Mise en page 1 21/05/2013 13:09 Page 1
I S S U E N ° 2 7 M A Y 2 0 1 3
remain expensive. Another solution might be for vertical contact on a
pad next the the Cu pillar. Some are using an area-array, membranelike
probe solution.
McCann also notes that the industry may need to go to dry etch at
finer geometries. At 20µm copper pillar, undercutting becomes an
issue by wet etch. Etching to remove the blanket UBM attacks the edge
of the bump and undercuts it, and with smaller pillars the undercut
becomes an increasing percentage of the smaller cross section, so
GLOBALFOUNDRIES is developing a dry etch process.
Chen is also concerned about re-work. “You can re-work solder, but
there’s no solution for copper pillar. It’s possible, but people just haven’t
looked at it yet.” He also warns to not count out competition from
older technologies. “Copper wire bonding will also be competition,” he
notes. “We used to think 1 mil would be its limit, but now it’s looking
at 0.5mil.” He notes that copper to copper bumpless bonding remains
in the research labs, with nothing demonstrated yet for high volume
production.
EMPC2013
Grenoble, France
European Microelectronics Packaging
Conference
September 9-12, 2013
EUROPOLE
Centre de Congrès
5-7 place Robert Schuman
Grenoble, France
Paula Doe for Yole Développement
William T. Chen, Fellow and Senior Technical Advisor,
ASE Group
Prior to joining the ASE Group, Bill was Director of the
Institute of Materials Research & Engineering (IMRE), in
Singapore. Previously, Bill worked for over thirty three years
performing various R&D and management positions at IBM
Corporation, where he was elected to the IBM Academy of
Technology. He is currently the co-chair of the International Technology Roadmap
for Semiconductors (ITRS) Assembly and Packaging International Technical
Working Group. Bill has been elected a Fellow of IEEE and a Fellow of ASME. In
2011, he was awarded the University Medal from Binghamton University
Dr. Raj Pendse, Vice President & Chief Marketing
Officer, STATS ChipPAC
He is responsible for marketing and business development of
the Company’s Advanced Technology products. Raj has been
with STATS ChipPAC for over 13 years in various leadership
positions in product engineering, technology and marketing.
Prior to joining STATS ChipPAC, Raj held various positions
in package engineering and R&D at National Semiconductor Corp and Hewlett-
Packard Labs. Raj completed his BS in Materials Science from IIT Bombay with
Top in Class honors and his Doctorate in Materials Science from UC Berkeley.
Registration and full programme on
www.empc2013.com
SPONSORS
David McCann, Vice President of Packaging,
GLOBALFOUNDRIES
Dave is responsible for Packaging R+D, interconnect
development, and back-end strategy and implementation.
David started at GLOBALFOUNDRIES in 2011.
Prior to GLOBALFOUNDRIES, David worked at Amkor
Technology for 11 years, most recently leading the BGA, Flip
Chip and MEMS product groups. He also led cross-functional teams in various
areas including networking product strategy and mobile product development.
David McCann received his Masters in Engineering Management from the Santa
Clara University in 1985 and his BS in Ceramic Engineering from the University
of Illinois in 1981.
MEDIA SPONSORS
PARTNERS
E urope

M A Y 2 0 1 3 I S S U E N ° 2 7
YOLE ASKS
Keeping up with the industry
heavyweights
IBM may have invented flip chip and Intel may have brought it to the worlds
microprocessors, but FCT, through its low cost processing technologies brought
it to hand held products in the early 2000’s.
Ted Tessier, Chief
Technical Officer,
FlipChip International
FlipChip Int (FCI) began in 1996 as FlipChip
Technologies (FCT), a joint venture between
Delco electronics and Kulicke and Soffa
(K&S). By modifying the Delco flip chip (FC)
process, FCT was able to develop and license what
quickly became the standard for flip chip bumping
across the world. All of the major assembly
houses including Amkor, ASE, STATS ChipPAC and
Siliconware ran the FCT process.
In 1998 FCT developed and patented the worlds
first wafer level chip sized package (WLCSP), the
Ultra CSP TM . In the early 2000’s estimates were
that > 80% of cell phones contained FC or WLP
parts derived from FCT processes.
In 2004 RoseStreet Labs, a private R&D company
based in Phoenix acquired FCT and renamed it
FlipChip Int. Through the years FCI has managed to
stay abreast of leading edge technologies and keep
up with the industry “heavyweights”. iMicronews
recently had the opportunity to have a one-on-one
with current CTO Ted Tessier to see where they
stood on copper pillar bumping (CPB).
Yole Développement: Is your organization
manufacturing CPB technology? If yes can
you share how long you have been doing this
and describe the technology for us?
Ted Tessier: FCI’s Cu pillar bumping process was
qualified in 2007 and in volume production since
2011. We offer a Standard Cu Pillar Bump for
applications with bump pitches of 150 microns or
less and our Nano-Pillar TM technology intended for
sub-100 micron pitch applications.
Our proprietary and patent pending technology is
based on a solder paste printed solder cap. This
approach enables a very broad range of solder
alloys to be used vs traditional electroplated
solder caps used by our competitors. This allows
the Cu Pillar bump to be readily tailored to the
reliability requirements of particular applications (i.e.
automotive, hand-held consumer products etc…). A
broad range of solder options have been qualified
including High-Pb, Sn/Pb eutectic, Sn/Ag eutectic,
pure Sn as well as High and Low Ag solder caps.
For SiP packaging, a single solder alloy solution
such as SAC305 or SAC405 is enabled.
Solder capped pillar bump provides substantially
improved bump height uniformity as a result of
the inherent ability of the paste printed cap to
compensate for Cu pillar plating variation. This is
particularly important in device applications that
require a range of different pillar bump sizes to
balance the localized on-chip interconnection
density / finer pitch requirements with improved
thermal performance by well-placed large racetrack
or breadloaf shaped bumps.
YD: Has CPB become mainstream technology ?
TT: Cu pillar bump technology has been a
mainstream technology in high performance
microprocessors for many years. Over the past
half decade or so, the adoption of Cu pillar bumping
for mid-range device applications has become
common. More recently, Cu pillar is starting to
be adopted selectively within the RF space, most
commonly for applications that require higher
levels of electrical performance.
FCI’s copper pillar bump coplanarity: across a broad range of bump sizes
(Courtesy of FlipChip International)
10
3 D P a c k a g i n g

I S S U E N ° 2 7 M A Y 2 0 1 3
35um diameter pillars,
23um in height, 50um pitch
75um diameter pillars,
40um in height, 100um pitch
FCI’s NANOPillar TM bumps for Sub-100 micron pitch applications (Courtesy of FlipChip International)
YD: Can you discuss the capacity you have in
place for CPB.
TT: FCI has in excess of 2000 wafers per month of
Cu pillar bumping capacity at our Phoenix, Arizona
facility with additional capacity coming on line in
2013 to approximately 4000 wafers per month.
This Cu Pillar bumping capacity expansion is
largely being driven by RF SiP module applications.
YD: What product or applications are your
customers using this interconnect technology
for ?
TT: FCI’s Cu pillar bumping customers use our
technology primarily for flip chip on leadframe and
flip chip on laminate SiP applications. An increasing
number of our customers are considering the use
of Cu pillar bumps for flip chip on silicon or flip chip
on glass applications. Most of the applications that
we have supported to date are either MEMS or
MEMS-like types of applications.
Most of our Cu pillar bumping applications either
involve capillary flow underfills or mold capping
flows such as in Flip Chip on Leadframe, that enables
simultaneous underfilling of flip chip attached die.
YD: What about reliability vs standard
underfilled FC technology ?
TT: Underfilled Cu pillar bumps provide package
level reliability that is equivalent or exceeds that
of all-solder based flip chip technologies. The
stiffness of Cu pillars relative to solder balls also
improves the reliability of Cu low K and other
fragile device structures.
www.flipchip.com
“Thermo
compression
bonding of Cu pillar
bumps is becoming
increasingly
common with
pitches as low as
45 microns,” says
Ted Tessier.
YD: What are you seeing in terms of
thermocompression vs reflow bonding ? At
what dimensions do customers use either
bonding technique ?
TT: Most of the flip chip on leadframe or flip chip
on laminate applications that we support involve
reflow flip chip attach to the substrate with flux
dipping down to minimum pitches of approximately
60 microns. For flip chip on silicon applications,
thermocompression bonding of Cu pillar bumps is
becoming increasingly common with pitches as low
as 45 microns currently running in high volume
production.
YD: Are your customers using underfill with
your CPB technology ?
TT: Yes, most of our customers use underfills to
enhance the reliability of next level interconnects.
Even for flip chip on silicon applications, where
thermomechanical considerations are less of a
consideration, they tend to use underfills.
3 D P a c k a g i n g
Ted Tessier, Chief Technical Officer,
FlipChip International
Ted has more than 25 years of
experience in the semiconductor
packaging industry and a comprehensive
industry perspective based on
senior engineering and management
positions at Nortel, Motorola, Biotronik,
AMKOR, STATS ChipPAC and FCI. He
has published actively and is well
known in the industry for his work
in the areas of advanced packaging
technologies including wafer bumping,
multichip modules / System in Package
technologies, WLCSPs, flip chip,
3 D packaging and embedded die
technologies.
11

M A Y 2 0 1 3 I S S U E N ° 2 7
A CLOSER LOOK
Will CPB be the next evolution of FC?
Microbumping, a.k.a. Copper Pillar Bumping appears to be the next evolution of flip
chip technology. Is this technology really mainstream ? What is its status today?
3D Packaging decided we should take – A Closer Look
D
The concept of interconnecting a chip in a
face down or “flip chip” (FC) orientation
can be traced back to IBM’s introduction of
their system 360 mainframe computer in 1964.
In the 1970s Delco Electronics developed FC
for automotive applications but in general, for
the next two decades FC was mainly confined
to high end main frame computers (IBM, NEC,
Fujitsu, Hitachi) because of reliability limitations
due to the mismatch between the coefficient of
thermal expansion (CTE) of Silicon (Si), solder and
substrate (ceramic, PCB).
As transistors continued to shrink, the increased
number of circuits per chip required more I/O which
eventually caught up with traditional IC designs
where pads were placed on the periphery to allow
interconnection by wire bonding to a lead frame.
It was obvious that higher I/O counts could only be
obtained by moving to area array packaging and
that required flip chip.
The development of lower cost sputtered UBMs
and lower cost stencil printed solder deposition
technology at FCT (1996-1998) in combination with
the IBM Japan revelation (1992) that underfilled
bumping could be used reliably on laminate,
opened the door for widespread adoption of this
high performance interconnection technology in
the late 1990’s.
The FCT “flex-on-cap” and “Ultra CSP” technologies
were licensed by all the key assembly houses as
they initiated production in 1999 - 2001 including:
P
ASE, Amkor, STATS ChipPAC, SPIL and others.
Most of the world’s production is still done today
using these or similar technologies.
But today, in order to deliver even higher
interconnect densities, i.e. “micro-bumping”, the
industry is having to adopt Copper pillar bumping
(CPB). Is this technology really mainstream? What
is its status today? 3D Packaging decided we
should take “A Closer Look”.
We have sought the input experts from several
different segments of the industry infrastructure
Manufacturing capacity
Bob Lanzone notes that “Amkor was the first OSAT
to develop and create HVM for this technology and
put large scale capacity in place to serve numerous
customers in 2010…We have shipped over 200
million units thus far”. In terms of capacity,
Lanzone states that Amkor has “…30K 300 mm
wafers per month CPB capacity” and a packaging
capacity of 15 MM units per month.
Mike Ma, VP of Corporate R&D for Siliconware
Precision Industries (SPIL), indicates that SPIL
has been in CPB production for “…over 2 years”.
Ma noted that their current capacity is 20K units/
month with plans to expand to 60K units/month in
4Q 2013. Ma sees CPB already being “mainstream…
especially in communication application devices.”
Remi Yu, Deputy Director of marketing at foundry
UMC, does not have wafer bumping in house
but rather “…collaborates with qualified OSATs
to provide bump solutions to our customers…”.
Yu notes that “…some customers [are] already
defining Cu pillar bump as the process of record at
28 nm node”.
UBM
TH
Copper pillar bump advantages
Al pad
Passivation
Si Wafer
Feature
Dimension
Pitch (P)
50-100um
Cu Pillar Diameter (D) 20-50um
Total height (TH)
30-45um
TI / Amkor copper pillar bump design rules (Courtesy of Texas Instruments and Amkor)
12
Our experts pretty much agree on the advantages
of CPB. SPIL’s Ma points to “…fine pitch, higher
standoff after assembly (which means better
reliability) and higher current carrying capability
as compared to a typical solder bump”. Yu sees
“…tighter pitch, better bump electromigration
(EM), higher speed signal propagation and better
thermal performance” as the key attributes. Dave
Stepniak, Packaging Development Manager at TI,
Amkor’s technology development partner, says
TI’s interests include tighter pitch, better EM
performance and scalability as key factors.
3 D P a c k a g i n g

I S S U E N ° 2 7 M A Y 2 0 1 3
Underfilling
When it comes to underfilling Yu informs us that
their customers have qualified capillary underfills
and that no flow and wafer applied underfills are
“under evaluation but not yet ready for mass
production”. Amkor Lanzone agrees adding that
“...pre applied underfills are currently under
development”. Ma concurs that standard capillary
underfills are now being used but adds that “…for
gaps

M A Y 2 0 1 3 I S S U E N ° 2 7
A CLOSER LOOK
The evolution of flip chip
packaging
Flip chip (FC) has had a pronounced impact on advanced packaging but do we
all know when and where these historic technology developments occurred? 3D
Packaging decided to take …a closer look.
IBM introduces flip chip
IBM introduced the FC concept in 1964 on the
IBM System 360 mainframe computer with solder
coated copper balls. In 1969 they introduced
solid solder balls - i.e. the controlled collapse chip
connection (C-4).
Intel eliminates resistance to new FC
processing technologies
The initial resistance to accept these non IBM
technologies was alleviated in 1999 when
Intel announced the use of Ti/Ni UBM for their
microprocessor packaging technology.
Redistribution - Area array FC from
chips designed with peripheral pads
One impediment to the use of FC was the lack of
FC designed chips. This was addressed in 1994
by Chanchani and co-workers who developed
redistribution layer technology (RDL).
IBM logic chip circa 1970 (Courtesy of IBM)
For the next two decades FC was mainly confined
to ceramic packaging in high end main frame
computers due to the CTE mismatch between Si
vs PCB laminates.
Underfilling – the key to reliability
Redistribution requires secondary passivation (thin
film polymers such as BCB and PI) and metallization
(typically Cu or Al) to reroute the peripheral pads
to a looser pitch area array configuration.
Aluminum or Copper
Redistribution
Line
Second passivation
Solder
Primary passivation
Terminal
In 1987 Hitachi revealed that FC die mounted in
ceramic packages had better reliability when the
area surrounding the solder balls was encapsulated
with an epoxy “underfill”. In 1992, Tsukada of
IBM Japan reported that FC could be reliably
used on PWB laminate if the chips were similarly
underfilled.
Silicon
Bond Pad
Active Circuits
“We have come
a long way since
IBM introduced
the flip chip
concept in 1964,”
says Dr Philip Garrou.
Driving down the processing cost –
FCT and Unitive
During the 1990’s lower cost bumping processes
were developed by the Microelectronics Center of
NC [MCNC] and its spin out company Unitive Inc
and the joint venture of Delco and KNS, Flip Chip
Technologies (FCT). Their developments of lower
cost UBMs (FCT - Al/Ni-V/Cu; Unitive - Ti/Cu/Ni)
and lower cost solder deposition technologies (FCT
- stencil printing; Unitive - plating) and their use of
redistribution (see later discussion) in combination
with the Tsukada revelation that bumping could
be used reliably on laminate, opened the door for
widespread acceptance of FC.
Redistribution (cross section (Top) and top
down (Bottom)) (Courtesy Unitive Electronics)
Wafer Level Packaging (WLP)
The next major breakthrough came with the
concept of wafer level packaging. WLP describes
a package which is fully fabricated on the wafer
before dice and subsequent surface mount.
14
3 D P a c k a g i n g

I S S U E N ° 2 7 M A Y 2 0 1 3
Cu RDL
Copper post /
barrier layer
PI Encaspulant SiN Solder Ball
Fujitsu SuperCSP (Courtesy of Fujitsu)
The first descriptions of this concept were by
Chanchani. The first commercialization of such a
product was by FCT which introduced the UltraCSP
in 1998. Over time the nomenclature changed from
mini-BGA, to wafer level chip scale package (WL-
CSP), to the simpler “wafer level package” or WLP.
WLP was reviewed in 2000.
Copper pillar technology
The concept of copper pillar bump stems from the
Fujitsu Super CSP package which placed solder
on top of copper pillars to increase the standoff
height of the solder bumps and thus the package
reliability. In later years this concept was used
to increase the density, reliability and electrical
performance when compared to standard FC.
In 2006, it was revealed that Intel had replaced
its traditional SnPb flip chip solder bumps with a
combination copper pillar/SnPb joint for its 65nm
Yonah and Pressler processors. In 2010, Texas
Instruments and Amkor announced the HVM of
copper pillar flip chip packages.
Dr. Phil Garrou for Yole Développement
3DIC technology is seen today
as a new paradigm for the future
of the semiconductor industry
2.5D, 3DIC and TSV Interconnect
Patent Landscape Analysis
Discover the NEW report on
www.i-Micronews.com/reports

M A Y 2 0 1 3 I S S U E N ° 2 7
ANALYST CORNER
Mainstream flip chip bumping starts
to move to copper pillars
Copper pillars and micro bumps will soon re-shape the flip chip market and supply
chain, as mobile processors, memory, and non-mainstream CMOS devices start
to require smaller geometries, higher I/O counts, higher bandwidth, and better
thermal management. That will propel 9% growth for the flip chip packaging
market through 2018, with most of that growth driven by the emerging copper
technologies.
Lionel Cadix,
Market & Technology
Analyst, Advanced
Packaging,
Yole Développement
The $20 billion flip chip market is poised for
9% CAGR to reach some $35 billion by 2018.
The big growth driver will be the transition to
copper pillar bumping, which will drive a 19% CAGR
in flip chip wafers processed. That means a 3X jump
in flip chipped (12” eq) wafers, to ~40 million a year
in the next 6 years—and almost all of the growth
--those 26 million additional wafers a year-- will use
copper pillars or micro-bumps, as copper comes to
increasingly dominate the flip chip market. Leadfree
solder will see healthy growth for the next year
or two as it replaces Sn/Pb solder, but demand will
start to level off in 2015-2016. Gold stud and plated
bumping will see little new investment or adoption.
We expect more than 50% of bumped wafers to use
copper pillars as early as next year, and copper to
quickly take over more than two thirds of the flip
chip bumping market by volume within a few years
thereafter, as a perfect storm of demand for higher
density, higher performance interconnect develops.
Demand will come from a variety of applications.
In 2012, logic for personal computers and laptops
accounted for more than half the flip chip bumping
market, with much of the rest used in mobile
phones and high performance computers. But
that mix will soon change as 28nm devices need
higher density connections than possible with
solder bumps, with demand driven especially by
application processors for mobile phones, and
mobile applications will quickly become the main
driving market for copper pillars. Next application
will likely be memory, which we also expect to start
to move quickly to copper pillars in the next couple
of years, starting with DDR4 and wide I/O, driven
by the need for fine pitch for high bandwidth and
high I/O count, to decrease delay and decrease
power consumption, as wire bonding parasitics
become more problematic. For memory below
Flip chip bumping wafer forecast*
Breakdown by bumping metallurgy (12’’eq wafers)
(Flip Chip report, Yole Développement, March 2013)
Millions
45
40
*3D µ-bumping included
35
30
Wafer count (12''eq)
25
20
15
Cu pillar
Lead free solder
Sn/Pb eutectic solder
Gold stud + plated
10
5
0
2010 2011 2012 2013 2014 2015 2016 2017 2018
16
3 D P a c k a g i n g

I S S U E N ° 2 7 M A Y 2 0 1 3
28nm, mass reflow will likely not be possible
for reliability reasons, so we will have to move
to copper pillar and thermal compression
bonding directly. Then 3DIC/2.5D interposers
will use copper pillar micro-bumping. Other
more-than-Moore applications will also move
to copper pillar for a variety of their own
reasons, from image sensors needing higher
density to power devices needing better
thermal performance.
Though the essential advantage of copper
pillars is the tighter pitch possible with the
straight-sided, high-aspect- ratio pillars and
their smaller micro-bump cousins compared
to the rounded form of solder bumps, the
reduction of noise from the larger spacing
between the pillars, and the better electrical
conductivity compared to solder also improve
performance. The downside, of course, is
the higher cost and the immaturity of some
of the processes, particularly probe and test.
Progress will also be needed on finer precision
in placement and bonding, and faster bonding
with greater pressure. But we see few viable
alternatives to copper pillar bumping going
forward, especially for big ICs, and those with
high numbers (~>800) of I/Os.
Everybody adds capacity, looks at
thermal compression bonding
This growing demand is spurring investment
across the value chain. Intel has long had
the biggest copper bumping capacity, but
foundries and OSATs are also both now
investing aggressively, with recent investment
by Samsung and TSMC on the foundry side,
and Amkor and ASE on the OSAT side, driven
primarily by 28nm CMOS. Most aggressive
of all is PTI in Taiwan, who is investing some
$300M over 2012-2014 to build and equip the
world’s first fully dedicated fab for advanced
bumping, to support its major customer
Micron, but also to serving fabless customers
like Qualcomm and non IC applications like
MEMS from Toshiba. We see a 31% CAGR
in additional copper pillar capacity brought
online from 2010 to 2014, to bring it to 9
million (12” eq) wafers a year. The industry’s
copper bumping facilities have recently been
running at ~88% capacity. This expanding
cast of suppliers will expand availability of
Network (Switch,
Router, Appliance)
298 779
2%
Game stations
504 135
4%
Feature Phone
555 129
4%
Desktop PC Screen
590 940
5%
Tablet
212 999
2%
HPC
791 256
6%
Smartphones
1 163 752
9%
copper pillar bumping to more users, and
could spur a variety of solutions to bringing
down costs.
The leading edge of production is now at
~40µm pitch, with companies like ASE,
STATS ChipPAC, TSMC and Samsung all
demonstrating that density. Mobile processors
are using anywhere from 100µm down to
40µm pitch density. While pushing out mass
reflow as long as possible will help keep down
costs, warpage of the substrate starts to
become a problem with the finer pillars, so
from 40µm or so we think most producers
will use thermal compression bonding with
pre-applied under fill. By the 22nm node
and below the extra low-k dielectric likely
won’t withstand mass reflow so will have
“We expect more than 50% of bumped wafers to use
copper pillars as early as next year,” says Lionel Cadix.
2012 Flip chip wafer start*
Breakdown by end product (12’’eq wafers)
(Flip Chip report, Yole Développement, March 2013)
Base stations
180 327
2%
to be bonded by thermal compression. We
expect to see a massive move to thermal
compression bonding in the next several
years. That will require pre-applied underfill
to hold the die in place for bonding. That
underfill is easier to apply with consistent
quality, but is more expensive. Biggest hurdle
to tighter pitches remains the accuracy of the
pick and place equipment at high throughput.
Main option for cost reduction of flip chip will
be the substrate, which accounts for some
35% of total middle end process costs, with
RDL and passivation, assembly, probe and
final test accounting for only some 14%-18%
Set-Top Box and
Hybrid Set-Top Box
177 625
1%
Smart TV & LCD TV
1 491 188
12%
Server
172 784
1%
Other end applications
270 474
2%
Laptop
3 662 163
29%
Desktop PC
2 695 375
21%
*3D μ-bumping included
each. Higher volumes could help reduce costs,
as could optimization of designs.
Low cost stud bumping still has a role as a
kind of bump, and is being adopted by things
like image sensors and power amplifiers as
a low cost solution for better performance
than wire bonding. We think, however, that
this is a transition phase, and many of these
applications will convert to copper microbumps
as that technology becomes more
mainstream and affordable.
Eventually, of course, bumps of any sort
will not offer the density or performance
demanded, and leading edge devices will
move to direct bumpless copper-to-copper
connections. But that technology is still in the
R&D labs, and we do not expect to see any
production until after 2018.
Note that for this updated forecast from
our recent report on flip chip, we added
consideration of silicon- to- silicon microbumping
and high power LEDs. We based the
forecasts on our new top-down packaging
model that looks at the ICs used across nine
major application markets (autos, computers,
phones…) and the packaging platforms used
for each.
www.yole.fr
Dr Lionel Cadix joined Yole Développement after the
completion of several projects linked to the
characterization and modeling of high density TSV
and 3DIC chip stacking in collaboration with CEA-Leti
and STMicroelectronics during his PhD. He is author
of several publications and 8 patents in the field of
3D Integration.
3 D P a c k a g i n g
17

M A Y 2 0 1 3 I S S U E N ° 2 7
EVENT REVIEW
“The fabless model has proven to
be very successful”, comments
Yole Développement
With more than 75 attendees at Successful Semiconductor Fabless 2013, Yole
Développement & Serma Technologies announce the 2014 edition.
The fabless model has existed in the
semiconductor sector for many years and has
proven to be very successful.
world, the business models evaluation: how we
could select the best one - which criteria we should
follow – when we should reevaluated them…
From April 10 - 12 in Paris, Yole Développement
and Serma Technologies gathered 75+ attendees
for Successful Semiconductor Fabless 2013 (SSF
2013), an event featuring fruitful discussions,
constructive debates and invaluable networking
times centered on the fabless model. SSF 2013
included key industrial speakers such as: Aptasic,
Amkor Technology, ASE, CEA-LETI, CSEM, Delta
Microelectronics, FEI Europe, GaN Systems, imec,
Mikrosens Elektronik, Nanium, Serma Technologies
and Yole Développement … Abstracts and bios
are available at www.ssf2013.fr/program.html. To
receive the presentations, please contact Sandrine
Leroy (leroy@yole.fr).
Yole Développement and Serma Technologies have
decided to build on 2013’s success and are already
looking forward to Successful Semiconductor
Fabless 2014.
Next year’s edition will take place in Paris, with a
focus on MEMS. Today, only a handful of foundries
can answer the MEMS fabless model’s latest demands.
But what about tomorrow?
“Today, the top 12 fabless semiconductor companies
own 80% of the market”, explains Christophe
Fitamant, Sales & Marketing Director at Yole
Développement. Due to their long-running, growing
success, we’ve seen the emergence of fabless
companies in other sectors, such as MEMS, Sensors,
and Power Electronics. “This shows that fabless
companies are essential to semiconductor industry
development as they are key technology drivers”,
says Pascal MATOSEVIC, Sales & Marketing Director
at Serma Technologies.
In fact, "going fabless" has become a strategic
choice. During SSF 2013, powerful discussions
set up and many topics have been developed: the
diversity of business models in the semiconductor
For more information:
• Sandrine Leroy (leroy@yole.fr)
• Pascal Matosevic (p.matosevic@serma.com)
• www.ssf2013.fr
18
3 D P a c k a g i n g

Watch it now
Editorial Webcast available today
2013 PROGRAM:
June 11
Silicon Microfluidics:
Myth or Reality?
July 9
IR imagers:
How cost decrease
will generate
new markets
Non mainstream packaging in
MEMS, LED, Power Electronics…
Derivative applications (MEMS, LEDs …) are source
of technological innovations for advanced packaging.
Hosted by:
For more information and to register, please go to
www.i-micronews.com/webcasts.asp or click here
Powered by:

M A Y 2 0 1 3 I S S U E N ° 2 7
Networking Day
SEMI Networking Day
Focus on Packaging - Key for System Integration
27 June 2013, Vila do Conde - Porto (Portugal), www.semi.org/seu
The Networking Day is a SEMI Europe initiative to support companies,
start-ups, laboratories involved in Fan Out Wafer Level Packaging and
Embedded Die in Laminate. Event includes visit of NANIUM’s clean room,
speed networking session and social evening program.
The Networking Day will feature invited speakers from:
• AT&S
• ASE Group
• Intel Mobile Communications
• NANIUM
Sponsored by:
• NXP
• STMicroelectronics
• TechSearch
• Yole Developpement
Hosted by:
Organized by:
SEMI Europe Grenoble Office
yguillou@semi.org
About Yole Développement
SEMI_Netw_Day_Porto_ad_186_132.indd 1 03.05.2013 15:10:49
Founded in 1998, Yole Développement has grown to become a group of companies providing marketing, technology and strategy consulting, media in
addition to corporate finance services.
With a strong focus on emerging applications using silicon and/or micro manufacturing, Yole Développement group has expanded to include more than 50 associates
worldwide covering MEMS, Compound Semiconductors, LED, Image Sensors, Optoelectronics, Microfluidics & Medical, Photovoltaics, Advanced Packaging,
Nanomaterials and Power Electronics. The group supports industrial companies, investors and R&D organizations worldwide to help them understand
markets and follow technology trends to develop their business.
CONSULTING
• Market data, market research & marketing analysis
• Technology analysis
• Reverse engineering & costing services
• Strategy consulting
• Patent analysis
More information on www.yole.fr
FINANCIAL SERVICES
• Mergers & Acquisitions
• Due diligence
• Fundraising
• Coaching of emerging companies
• IP portfolio management & optimization
More information on www.yolefinance.com
CONTACTS
For more information about :
• Consulting Services: Christophe Fitamant (fitamant@yole.fr)
• Financial Services: Géraldine Andrieux-Gustin (Andrieux@yole.fr)
• Reports: David Jourdan (jourdan@yole.fr)
• Media & Communication: Sandrine Leroy (leroy@yole.fr)
REPORTS
• Collection of technology & market reports
• Manufacturing cost simulation tools
• Component reverse engineering & costing analysis
• Patent analysis
MEDIA
• Online disruptive technologies website: www.i-micronews.com
• Editorial webcasts program
• Six magazines: Micronews - MEMS Trends – 3D Packaging – iLED –
Power Dev' - New in 2013: Image Sensors Industry
• Communication & Webcasts services
Editorial Staff
Managing Editor: Jean-Christophe Eloy - Editor in chief: Dr Eric Mounier - Editors:
Lionel Cadix, Paula Doe, Christophe Fitamant, Phil Garrou - Media & Communication
Manager: Sandrine Leroy - Media & Communication Coordinator: Camille Favre - Production:
atelier JBBOX
20 3 D P a c k a g i n g