May 2013 - I-Micronews

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M A Y 2 0 1 3 I S S U E N ° 2 7 YOLE ASKS Keeping up with the industry heavyweights IBM may have invented flip chip and Intel may have brought it to the worlds microprocessors, but FCT, through its low cost processing technologies brought it to hand held products in the early 2000’s. Ted Tessier, Chief Technical Officer, FlipChip International FlipChip Int (FCI) began in 1996 as FlipChip Technologies (FCT), a joint venture between Delco electronics and Kulicke and Soffa (K&S). By modifying the Delco flip chip (FC) process, FCT was able to develop and license what quickly became the standard for flip chip bumping across the world. All of the major assembly houses including Amkor, ASE, STATS ChipPAC and Siliconware ran the FCT process. In 1998 FCT developed and patented the worlds first wafer level chip sized package (WLCSP), the Ultra CSP TM . In the early 2000’s estimates were that > 80% of cell phones contained FC or WLP parts derived from FCT processes. In 2004 RoseStreet Labs, a private R&D company based in Phoenix acquired FCT and renamed it FlipChip Int. Through the years FCI has managed to stay abreast of leading edge technologies and keep up with the industry “heavyweights”. i<strong>Micronews</strong> recently had the opportunity to have a one-on-one with current CTO Ted Tessier to see where they stood on copper pillar bumping (CPB). Yole Développement: Is your organization manufacturing CPB technology? If yes can you share how long you have been doing this and describe the technology for us? Ted Tessier: FCI’s Cu pillar bumping process was qualified in 2007 and in volume production since 2011. We offer a Standard Cu Pillar Bump for applications with bump pitches of 150 microns or less and our Nano-Pillar TM technology intended for sub-100 micron pitch applications. Our proprietary and patent pending technology is based on a solder paste printed solder cap. This approach enables a very broad range of solder alloys to be used vs traditional electroplated solder caps used by our competitors. This allows the Cu Pillar bump to be readily tailored to the reliability requirements of particular applications (i.e. automotive, hand-held consumer products etc…). A broad range of solder options have been qualified including High-Pb, Sn/Pb eutectic, Sn/Ag eutectic, pure Sn as well as High and Low Ag solder caps. For SiP packaging, a single solder alloy solution such as SAC305 or SAC405 is enabled. Solder capped pillar bump provides substantially improved bump height uniformity as a result of the inherent ability of the paste printed cap to compensate for Cu pillar plating variation. This is particularly important in device applications that require a range of different pillar bump sizes to balance the localized on-chip interconnection density / finer pitch requirements with improved thermal performance by well-placed large racetrack or breadloaf shaped bumps. YD: Has CPB become mainstream technology ? TT: Cu pillar bump technology has been a mainstream technology in high performance microprocessors for many years. Over the past half decade or so, the adoption of Cu pillar bumping for mid-range device applications has become common. More recently, Cu pillar is starting to be adopted selectively within the RF space, most commonly for applications that require higher levels of electrical performance. FCI’s copper pillar bump coplanarity: across a broad range of bump sizes (Courtesy of FlipChip International) 10 3 D P a c k a g i n g
I S S U E N ° 2 7 M A Y 2 0 1 3 35um diameter pillars, 23um in height, 50um pitch 75um diameter pillars, 40um in height, 100um pitch FCI’s NANOPillar TM bumps for Sub-100 micron pitch applications (Courtesy of FlipChip International) YD: Can you discuss the capacity you have in place for CPB. TT: FCI has in excess of 2000 wafers per month of Cu pillar bumping capacity at our Phoenix, Arizona facility with additional capacity coming on line in <strong>2013</strong> to approximately 4000 wafers per month. This Cu Pillar bumping capacity expansion is largely being driven by RF SiP module applications. YD: What product or applications are your customers using this interconnect technology for ? TT: FCI’s Cu pillar bumping customers use our technology primarily for flip chip on leadframe and flip chip on laminate SiP applications. An increasing number of our customers are considering the use of Cu pillar bumps for flip chip on silicon or flip chip on glass applications. Most of the applications that we have supported to date are either MEMS or MEMS-like types of applications. Most of our Cu pillar bumping applications either involve capillary flow underfills or mold capping flows such as in Flip Chip on Leadframe, that enables simultaneous underfilling of flip chip attached die. YD: What about reliability vs standard underfilled FC technology ? TT: Underfilled Cu pillar bumps provide package level reliability that is equivalent or exceeds that of all-solder based flip chip technologies. The stiffness of Cu pillars relative to solder balls also improves the reliability of Cu low K and other fragile device structures. www.flipchip.com “Thermo compression bonding of Cu pillar bumps is becoming increasingly common with pitches as low as 45 microns,” says Ted Tessier. YD: What are you seeing in terms of thermocompression vs reflow bonding ? At what dimensions do customers use either bonding technique ? TT: Most of the flip chip on leadframe or flip chip on laminate applications that we support involve reflow flip chip attach to the substrate with flux dipping down to minimum pitches of approximately 60 microns. For flip chip on silicon applications, thermocompression bonding of Cu pillar bumps is becoming increasingly common with pitches as low as 45 microns currently running in high volume production. YD: Are your customers using underfill with your CPB technology ? TT: Yes, most of our customers use underfills to enhance the reliability of next level interconnects. Even for flip chip on silicon applications, where thermomechanical considerations are less of a consideration, they tend to use underfills. 3 D P a c k a g i n g Ted Tessier, Chief Technical Officer, FlipChip International Ted has more than 25 years of experience in the semiconductor packaging industry and a comprehensive industry perspective based on senior engineering and management positions at Nortel, Motorola, Biotronik, AMKOR, STATS ChipPAC and FCI. He has published actively and is well known in the industry for his work in the areas of advanced packaging technologies including wafer bumping, multichip modules / System in Package technologies, WLCSPs, flip chip, 3 D packaging and embedded die technologies. 11
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May 2013 - I-Micronews

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