May 2013 - I-Micronews

I S S U E N ° 2 7 M A Y 2 0 1 3
28nm, mass reflow will likely not be possible
for reliability reasons, so we will have to move
to copper pillar and thermal compression
bonding directly. Then 3DIC/2.5D interposers
will use copper pillar micro-bumping. Other
more-than-Moore applications will also move
to copper pillar for a variety of their own
reasons, from image sensors needing higher
density to power devices needing better
thermal performance.
Though the essential advantage of copper
pillars is the tighter pitch possible with the
straight-sided, high-aspect- ratio pillars and
their smaller micro-bump cousins compared
to the rounded form of solder bumps, the
reduction of noise from the larger spacing
between the pillars, and the better electrical
conductivity compared to solder also improve
performance. The downside, of course, is
the higher cost and the immaturity of some
of the processes, particularly probe and test.
Progress will also be needed on finer precision
in placement and bonding, and faster bonding
with greater pressure. But we see few viable
alternatives to copper pillar bumping going
forward, especially for big ICs, and those with
high numbers (~>800) of I/Os.
Everybody adds capacity, looks at
thermal compression bonding
This growing demand is spurring investment
across the value chain. Intel has long had
the biggest copper bumping capacity, but
foundries and OSATs are also both now
investing aggressively, with recent investment
by Samsung and TSMC on the foundry side,
and Amkor and ASE on the OSAT side, driven
primarily by 28nm CMOS. Most aggressive
of all is PTI in Taiwan, who is investing some
$300M over 2012-2014 to build and equip the
world’s first fully dedicated fab for advanced
bumping, to support its major customer
Micron, but also to serving fabless customers
like Qualcomm and non IC applications like
MEMS from Toshiba. We see a 31% CAGR
in additional copper pillar capacity brought
online from 2010 to 2014, to bring it to 9
million (12” eq) wafers a year. The industry’s
copper bumping facilities have recently been
running at ~88% capacity. This expanding
cast of suppliers will expand availability of
Network (Switch,
Router, Appliance)
298 779
2%
Game stations
504 135
4%
Feature Phone
555 129
4%
Desktop PC Screen
590 940
5%
Tablet
212 999
2%
HPC
791 256
6%
Smartphones
1 163 752
9%
copper pillar bumping to more users, and
could spur a variety of solutions to bringing
down costs.
The leading edge of production is now at
~40µm pitch, with companies like ASE,
STATS ChipPAC, TSMC and Samsung all
demonstrating that density. Mobile processors
are using anywhere from 100µm down to
40µm pitch density. While pushing out mass
reflow as long as possible will help keep down
costs, warpage of the substrate starts to
become a problem with the finer pillars, so
from 40µm or so we think most producers
will use thermal compression bonding with
pre-applied under fill. By the 22nm node
and below the extra low-k dielectric likely
won’t withstand mass reflow so will have
“We expect more than 50% of bumped wafers to use
copper pillars as early as next year,” says Lionel Cadix.
2012 Flip chip wafer start*
Breakdown by end product (12’’eq wafers)
(Flip Chip report, Yole Développement, March 2013)
Base stations
180 327
2%
to be bonded by thermal compression. We
expect to see a massive move to thermal
compression bonding in the next several
years. That will require pre-applied underfill
to hold the die in place for bonding. That
underfill is easier to apply with consistent
quality, but is more expensive. Biggest hurdle
to tighter pitches remains the accuracy of the
pick and place equipment at high throughput.
Main option for cost reduction of flip chip will
be the substrate, which accounts for some
35% of total middle end process costs, with
RDL and passivation, assembly, probe and
final test accounting for only some 14%-18%
Set-Top Box and
Hybrid Set-Top Box
177 625
1%
Smart TV & LCD TV
1 491 188
12%
Server
172 784
1%
Other end applications
270 474
2%
Laptop
3 662 163
29%
Desktop PC
2 695 375
21%
*3D μ-bumping included
each. Higher volumes could help reduce costs,
as could optimization of designs.
Low cost stud bumping still has a role as a
kind of bump, and is being adopted by things
like image sensors and power amplifiers as
a low cost solution for better performance
than wire bonding. We think, however, that
this is a transition phase, and many of these
applications will convert to copper microbumps
as that technology becomes more
mainstream and affordable.
Eventually, of course, bumps of any sort
will not offer the density or performance
demanded, and leading edge devices will
move to direct bumpless copper-to-copper
connections. But that technology is still in the
R&D labs, and we do not expect to see any
production until after 2018.
Note that for this updated forecast from
our recent report on flip chip, we added
consideration of silicon- to- silicon microbumping
and high power LEDs. We based the
forecasts on our new top-down packaging
model that looks at the ICs used across nine
major application markets (autos, computers,
phones…) and the packaging platforms used
for each.
www.yole.fr
Dr Lionel Cadix joined Yole Développement after the
completion of several projects linked to the
characterization and modeling of high density TSV
and 3DIC chip stacking in collaboration with CEA-Leti
and STMicroelectronics during his PhD. He is author
of several publications and 8 patents in the field of
3D Integration.
3 D P a c k a g i n g
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