May 2013 - I-Micronews

M A Y 2 0 1 3 I S S U E N ° 2 7
A CLOSER LOOK
Will CPB be the next evolution of FC?
Microbumping, a.k.a. Copper Pillar Bumping appears to be the next evolution of flip
chip technology. Is this technology really mainstream ? What is its status today?
3D Packaging decided we should take – A Closer Look
D
The concept of interconnecting a chip in a
face down or “flip chip” (FC) orientation
can be traced back to IBM’s introduction of
their system 360 mainframe computer in 1964.
In the 1970s Delco Electronics developed FC
for automotive applications but in general, for
the next two decades FC was mainly confined
to high end main frame computers (IBM, NEC,
Fujitsu, Hitachi) because of reliability limitations
due to the mismatch between the coefficient of
thermal expansion (CTE) of Silicon (Si), solder and
substrate (ceramic, PCB).
As transistors continued to shrink, the increased
number of circuits per chip required more I/O which
eventually caught up with traditional IC designs
where pads were placed on the periphery to allow
interconnection by wire bonding to a lead frame.
It was obvious that higher I/O counts could only be
obtained by moving to area array packaging and
that required flip chip.
The development of lower cost sputtered UBMs
and lower cost stencil printed solder deposition
technology at FCT (1996-1998) in combination with
the IBM Japan revelation (1992) that underfilled
bumping could be used reliably on laminate,
opened the door for widespread adoption of this
high performance interconnection technology in
the late 1990’s.
The FCT “flex-on-cap” and “Ultra CSP” technologies
were licensed by all the key assembly houses as
they initiated production in 1999 - 2001 including:
P
ASE, Amkor, STATS ChipPAC, SPIL and others.
Most of the world’s production is still done today
using these or similar technologies.
But today, in order to deliver even higher
interconnect densities, i.e. “micro-bumping”, the
industry is having to adopt Copper pillar bumping
(CPB). Is this technology really mainstream? What
is its status today? 3D Packaging decided we
should take “A Closer Look”.
We have sought the input experts from several
different segments of the industry infrastructure
Manufacturing capacity
Bob Lanzone notes that “Amkor was the first OSAT
to develop and create HVM for this technology and
put large scale capacity in place to serve numerous
customers in 2010…We have shipped over 200
million units thus far”. In terms of capacity,
Lanzone states that Amkor has “…30K 300 mm
wafers per month CPB capacity” and a packaging
capacity of 15 MM units per month.
Mike Ma, VP of Corporate R&D for Siliconware
Precision Industries (SPIL), indicates that SPIL
has been in CPB production for “…over 2 years”.
Ma noted that their current capacity is 20K units/
month with plans to expand to 60K units/month in
4Q 2013. Ma sees CPB already being “mainstream…
especially in communication application devices.”
Remi Yu, Deputy Director of marketing at foundry
UMC, does not have wafer bumping in house
but rather “…collaborates with qualified OSATs
to provide bump solutions to our customers…”.
Yu notes that “…some customers [are] already
defining Cu pillar bump as the process of record at
28 nm node”.
UBM
TH
Copper pillar bump advantages
Al pad
Passivation
Si Wafer
Feature
Dimension
Pitch (P)
50-100um
Cu Pillar Diameter (D) 20-50um
Total height (TH)
30-45um
TI / Amkor copper pillar bump design rules (Courtesy of Texas Instruments and Amkor)
12
Our experts pretty much agree on the advantages
of CPB. SPIL’s Ma points to “…fine pitch, higher
standoff after assembly (which means better
reliability) and higher current carrying capability
as compared to a typical solder bump”. Yu sees
“…tighter pitch, better bump electromigration
(EM), higher speed signal propagation and better
thermal performance” as the key attributes. Dave
Stepniak, Packaging Development Manager at TI,
Amkor’s technology development partner, says
TI’s interests include tighter pitch, better EM
performance and scalability as key factors.
3 D P a c k a g i n g