May 2013 - I-Micronews

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M A Y 2 0 1 3 I S S U E N ° 2 7 A CLOSER LOOK The evolution of flip chip packaging Flip chip (FC) has had a pronounced impact on advanced packaging but do we all know when and where these historic technology developments occurred? 3D Packaging decided to take …a closer look. IBM introduces flip chip IBM introduced the FC concept in 1964 on the IBM System 360 mainframe computer with solder coated copper balls. In 1969 they introduced solid solder balls - i.e. the controlled collapse chip connection (C-4). Intel eliminates resistance to new FC processing technologies The initial resistance to accept these non IBM technologies was alleviated in 1999 when Intel announced the use of Ti/Ni UBM for their microprocessor packaging technology. Redistribution - Area array FC from chips designed with peripheral pads One impediment to the use of FC was the lack of FC designed chips. This was addressed in 1994 by Chanchani and co-workers who developed redistribution layer technology (RDL). IBM logic chip circa 1970 (Courtesy of IBM) For the next two decades FC was mainly confined to ceramic packaging in high end main frame computers due to the CTE mismatch between Si vs PCB laminates. Underfilling – the key to reliability Redistribution requires secondary passivation (thin film polymers such as BCB and PI) and metallization (typically Cu or Al) to reroute the peripheral pads to a looser pitch area array configuration. Aluminum or Copper Redistribution Line Second passivation Solder Primary passivation Terminal In 1987 Hitachi revealed that FC die mounted in ceramic packages had better reliability when the area surrounding the solder balls was encapsulated with an epoxy “underfill”. In 1992, Tsukada of IBM Japan reported that FC could be reliably used on PWB laminate if the chips were similarly underfilled. Silicon Bond Pad Active Circuits “We have come a long way since IBM introduced the flip chip concept in 1964,” says Dr Philip Garrou. Driving down the processing cost – FCT and Unitive During the 1990’s lower cost bumping processes were developed by the Microelectronics Center of NC [MCNC] and its spin out company Unitive Inc and the joint venture of Delco and KNS, Flip Chip Technologies (FCT). Their developments of lower cost UBMs (FCT - Al/Ni-V/Cu; Unitive - Ti/Cu/Ni) and lower cost solder deposition technologies (FCT - stencil printing; Unitive - plating) and their use of redistribution (see later discussion) in combination with the Tsukada revelation that bumping could be used reliably on laminate, opened the door for widespread acceptance of FC. Redistribution (cross section (Top) and top down (Bottom)) (Courtesy Unitive Electronics) Wafer Level Packaging (WLP) The next major breakthrough came with the concept of wafer level packaging. WLP describes a package which is fully fabricated on the wafer before dice and subsequent surface mount. 14 3 D P a c k a g i n g
I S S U E N ° 2 7 M A Y 2 0 1 3 Cu RDL Copper post / barrier layer PI Encaspulant SiN Solder Ball Fujitsu SuperCSP (Courtesy of Fujitsu) The first descriptions of this concept were by Chanchani. The first commercialization of such a product was by FCT which introduced the UltraCSP in 1998. Over time the nomenclature changed from mini-BGA, to wafer level chip scale package (WL- CSP), to the simpler “wafer level package” or WLP. WLP was reviewed in 2000. Copper pillar technology The concept of copper pillar bump stems from the Fujitsu Super CSP package which placed solder on top of copper pillars to increase the standoff height of the solder bumps and thus the package reliability. In later years this concept was used to increase the density, reliability and electrical performance when compared to standard FC. In 2006, it was revealed that Intel had replaced its traditional SnPb flip chip solder bumps with a combination copper pillar/SnPb joint for its 65nm Yonah and Pressler processors. In 2010, Texas Instruments and Amkor announced the HVM of copper pillar flip chip packages. Dr. Phil Garrou for Yole Développement 3DIC technology is seen today as a new paradigm for the future of the semiconductor industry 2.5D, 3DIC and TSV Interconnect Patent Landscape Analysis Discover the NEW report on www.i-<strong>Micronews</strong>.com/reports
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May 2013 - I-Micronews

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