Synchronous Latency Insensitive Design - ICS

Synchronous Latency Insensitive 

Design 

Christer Svensson and Anders Edman 

Linköping University 

Christer Svensson, ASYNC 2004 1

Outline 

• Introduction 

• Overview of wire properties 

• Architectural view of future systems 

• Synchronous Latency Insensitive Design 

• Multiple clocks 

• Conclusion 


Introduction 

The wire delay problem was recognized very early (Anceau 1982) 

Wire delay ~ L 2 /s 2 , Gate delay ~s α , s=feature size, α=1..2 

In spite of the “alarm” 1982, we still manage multigigahertz synchronous 

designs, BUT today with considerable problems. 

ASIC style designs normally limited to 300-500MHz clock, with severe 

“timing closure” problems. 

Multigigahertz designs very demanding full custom design style. 


Introduction 

Synchronous design paradigm VERY established – we need to keep. 

(Easy to keep track on exact timing of all events; predictable performance) 

Vast experience used to manage ever increasing complexity. 

Critical: Timing relations between clock and data 

Present solution: 

“Flat” clock distribution (skew-free clock) 

Does not solve problem with data delays 

clk 

Balanced clk net - no skew 

Wire delay still affects data 


Overview of wire properties 

Ground planes 

Twisted 

pair 

Cables 

Coaxial 

cable 

Microstrip 

Coplanar waveguide 

Circuit boards and chips 

We will concentrate on microstrip 

in the following 



Skin effect loss 

Higher frequencies - skineffekt 

Fields penetrate metal to skin-depth δ 

Resistance per unit length, r: 

r = r s 

ω 

Including current phase and low frequency resistance: 

Current flow, depth δ, (skin depth) 

r 

= rDC + rs 

1+ 

( j) ω 

Frequency dependence (dispersion) gives rise to signal distortion 



We discuss 2 wire properties in the following 

Delay (Latency) 

Capacity (Maximum data rate) 



Delay or latency, RC-wire 

High loss case (RC-case), r DC L/Z 0 >2ln2. Elmore delay good approximation: 

t 

d 

⎛ 

⎜ R 

⎝ 

⎛ C 

⎜ 

⎝ 2 

⎞⎞ 

⎟ 

⎠⎠ 

w 

( C + C + C ) + R + C ⎟ln 

2 

= 

S S w L w 

L 

Latency can be improved 

by repeaters 

Delay or latency, LC-wire 

Low loss case (LC-case), r DC L/Z 0


Capacity or maximum data rate 

T 

S(T) 

Single pulse 

Eye diagram 

Eye opening 

Eye opening = 2S(T)-1, S(t) step response, T symbol time 

We need a minimum opening for safe data detection, say 64% 

For long wires we may afford a simple equalizer, allowing 0% 



Capacity or maximum data rate 

RC-wire: Step response: 

S 

− 

2T 

R w 

( ) w C 

T = 1− 

e 

Eye opening of 64% yields S(T)=0.82 or T=0.85R w C w 

Max data rate 

LC-wire: Step response (skin effect): 

Max data rate, 

B 

1 

= 

T 

B = b 

= 

LC 

b 

RC 

A 

2 

L 

A 

2 

L 

S 

( T ) 

= 1− 

erf 

⎛ 

⎜ 

⎝ 

2Z 

ρµ 

0 

w 

0 

L 

T 

⎞ 

⎟ 

⎠ 



Note the difference between latency and data rate 

RC case 

t d 

T s >t d 

(wave pipelining, Xu 2003) 

LC case 

t d 

T s


Estimated data-rates 

Top metal 

chip wire 

10Gb/s 

@ 15mm 

Typical 

Board 

wire 

10Gb/s 

@ 0.5m 

Low level 

metal wire 

10Gb/s 

@ 1mm 

Low delay 

region 



Low level on-chip wires 

Wire delay limits diameter of synchronous block 

System partition – “Global Asynchronous Local Synchronous” 

Upper on-chip wires 

Low delay, high data-rate global communication 

Inter-block communication 

Circuit board wires 

Can be used at least to 10Gb/s per wire 

Facilitates very high on-board bandwidths 



On-chip local 

Future processes, feature size f=0.1 - 0.035 µm 

wire cross section ~3f 2 , for 0.1µm: 3·10 -14 m 2 

10Gb/s up to 1.25mm length 

1mm wire will have a delay of 26ps (26% of 10GHz clock cycle) 

We may use 10GHz clock frequency in fully synchronous block 

of diameter 1mm. Such a block can contain 250,000 gates. 

(Compare to Sylvester and Keutzler 50-100 kgates) 

Note that diameter scales as f 2 ; number of gates as f -2 

so 250 kgates is kept until 0.035µm (or further) at 10GHz. 



On-chip global 

Traditional alternative 

Automatic insertion of repeaters along long wires 

With wave pipelining allows >10Gb/s per wire 

Delays may exceed one clock cycle 

Utilizing upper thick metal layer 

Data rate >10Gb/s 

Delays close to velocity-of-light, still order of one clock cycle 



Upper wire/driver example 

Inverter in 0.18µm CMOS 

W n =88µm, w p =194µm, R S =20Ω 

Actual step response 

Step response 

without overdrive 

Step response, terminated 

3.5µm 

2µm 

Wire length 2cm 

4µm 12µm 

2µm x 4µm copper wire, low loss 

12µm spacing, X-talk


Upper wire/driver example 

Estimated performance (length 2cm) 

• Simulated velocity: 10 8 m/s (c 0 /3) 

• Simulated maximum data-rate 10Gb/s 

• Each link is 16 bit wide, 2 links carry 320Gb/s (bidirectionally) 

• Each 2 links need 544µm width 


Architectural view of future systems 

Chip 

On-chip global links 

Chip 

Synchronous 

blocks 

High speed 

board links 

Clock 



Chip 

On-chip global links 

Chip 

Challenges 


blocks 

Allow scaling of clock rates and bandwidths 

Mitigate synchronization and clock skew problems 

Keep an unchanged synchronous High speed design paradigm 

board links 

Clock 



Wire delays are inevitable: we must accept latency. 

The latency/delay problem should be managed at two levels 

• System level (predictability) 

• Implementation level (error-free) 



System level. 

Partition the system into blocks of limited size. 

(Preferably natural partition, processors, memories, IP-blocks etc.) 

We may define a system where only order of events is important. 

(“Classical” asynchronous, Patient systems (Carloni et al 1999)) 

We may then accept any latency between blocks. 

We may define a system with fixed latency between blocks. 

(If fixed latency is n clock cycles, the system is synchronous) 

We may then accept any latency < nT c between blocks. 



Implementation level (We must avoid synchronization errors) 

Use synchronizers with long decision time 

(extra latency, nonzero error probability) 

Use stoppable clocks to synchronize communication 

(Classical GALS, Chapiro 1984) 

Adapt clock phase to data (mesochronous clocks) 

(Mu 2001) 

Use FIFO’s to isolate clock regions 

(FIFO’s initialized with synchronizers, Chakraborty 2001) 

(FIFO’s initialized via system reset, Edman 2004) 



Implementation level, Examples 

Data in 

Choise of clock phase 

(Mu 2001) 

Metastab. 

detector 

Data out 

Rx clk 

FIFO solution 

(Chakraborty 2001, 

Edman 2004) 

Data in 

Write 

pointer 

Read 

pointer 

Data out 

Tx clk 

Rx clk 

“Circular” FIFO 


Synchronous Latency Insensitive Design 

Problem formulation 

Find a method to mitigate wire-induced latencies within a 

synchronous paradigm 



Concept 

Clock true model 

Fixed delays (n clk cycles) 

Communication links 

clk 


blocks 

Synthesis 

During synthesis we 

replace Fixed delays with 

synchronizing ports 

(elastic FIFOs) that absorb 

all link latencies and 

clock skews. 

Final design agree exactly 

with Clock true model 

independently of 

link delays and clock skews. 



System 

partition 

Design flow 

“Natural” partition (processors, memories, 

IP-blocks…) into isochronous regions 

Clock-true 

model & 

verification 

NEW: Insertion of dummy delays between 

isochronic regions. Clock-true verification. 

Synthesis & 

Back-end 

Replace dummy delays with elastic FIFO’s 

Timing 

verification 

Considerably easier, feedback can be avoided 



Implementation 

data 

reg 

reg 

data 

data 

strobe 

clk 

Example with three blocks 

and two links 

select 

Input 

counter 

strobe 

Output 

counter 

Local 

clock 

Synchronizing port 

Fixed nominal delay preset in counters 



Implementation 

System reset used as initialization mechanism (example n=2) 

clk 

Tx1 

rst 

written into 

FIFO(2) by strobe 

reset 

clk at root 

data at Tx1 

data at Rx 

Tx2 

read from FIFO(2) by 

Rx clk after 2 counts 

FIFO(2) 

clk at Rx 

Rx 

data in Rx 

Note that data relation to clk period number predictable 



Simulation 

clk 

Tx1 

Clk 

Tx1 out 

Rx1 in 

Tx2 out 

Rx2 in 

Rx1 out 

Rx2 out 

Rx1 in count 

Rx1 out count 

Rx2 in count 

Rx2 out count 

00 01 10 11 00 01 10 11 00 01 

10 11 00 01 10 11 00 01 10 11 00 01 

00 01 10 11 00 01 10 11 00 01 10 

10 11 00 01 10 11 00 01 10 11 00 01 

Rx 

Tx2 

0 20 ns 40 ns 60 ns 

Clk 

Tx1 out 

Rx1 in 

Tx2 out 

Rx2 in 

Rx1 out 

Rx2 out 

Rx1 in count 00 01 10 11 00 01 10 11 00 01 

Rx1 out count 10 11 00 01 10 11 00 01 10 11 

Rx2 in count 00 01 10 11 00 01 10 11 00 01 10 

11 

Rx2 out count 10 11 00 01 10 11 00 01 10 

0 20 ns 40 ns 60 ns 



Implementation example, receiver in 0.18µm CMOS 

f c =2.75GHz 

Area ≈ 3500 µm 2 

Data sent over 2mm wire 

Latency 2 cycles 

Rx clk delay 1 cycle 

Rx input 

Tx clk 

Rx clk 

(SPICE circuit level @110 o C) 

Reference data 

Read data 



New method to ease timing closure in large DSM chips 

• Correct clock-true verification before synthesis 

• Synchronous design paradigm and design tools kept 

• Implementation induced data delays and clock skews mitigated 

• Implementation in standard libraries 

• Full clock alignment between blocks 

• No synchronizers, no risk for metastability 


Multiple clocks 

Can a multiple clock system be synchronous? 

Example – rationally related clocks 

f c1 

f c2 =(2/3)f c1 

f= 

Synchronous to f c1 


Multiple clocks 

FIFO synchronization can be extended to 

rationally related clocks 

(FIFO used for mitigation of delays and introduced clock jitter) 

Chakraborty 2003, 

(Our proposal 2004) 

Write 

pointer 

Read 

pointer 

Jitter 

accepted 

Chakraborty extended his scheme to any clock frequency relation 


Conclusions 

Wire delays are inevitable 

Wire delays may be limited to velocity-of-light delays 

Synchronous blocks may include 250kgates @10GHz clock 

Delays must be managed at system level and implementation level 

Our proposed scheme facilitates: 

synchronous flow from system to implementation 

clock-true verification before synthesis 

mitigation of clock skews and data latencies 

“Synchronous” schemes can be extended to multiple clocks 


References 

F. Anceau, "A Synchronous Approach for Clocking VLSI Systems", IEEE J. Solid-State Circuits, Vol. 17, 

pp. 51-56, 1982. 

D. M. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems”, PhD Thesis, Stanford University, 

Oct. 1984. 

M. Afghahi and C. Svensson, “Performance of Synchronous and Asynchronous Schemes for VLSI Systems”, 

IEEE Trans. on Computers, Vol. 41, pp. 858-872, 1992. 

D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron", IEEE/ACM Int. Conference on 

Computer Aided Design 1998, Digest of Technical Papers, pp. 203-211, 1998. 

L. P. Carloni, K. L. McMillan, A. Saldanha and A. L. Sangiovanni-Vincentelli, "A Methodology for 

Correct-by-Construction Latency Insensitive Design", 1999 IEEE/ACM International Conference on 

Computer-Aided Design, Digest of Technical Papers, pp. 309-315, Nov. 1999. 

F. Mu and C. Svensson, ”Self-tested self-synchronization circuit for mesochronous clocking”, IEEE Trans. on 

Circuits and Systems II: Analog and Digital Signal Processing, vol 48, pp. 129 – 140, Feb. 2001 

A. Chakraborty and M. R. Greenstreet, "A Minimal Source-Synchronous Interface", 15 th Annual IEEE 

International ASIC/SOC Conference, pp. 443-447, Sept. 2002. 

C. Svensson, “Electrical Interconnects Revitalized”, IEEE Trans. on Very Large Scale Integration, vol. 10, 

pp. 777-788, Dec. 2002. 

J. Xu and W. Wolf, “A Wave-Pipelined On-chip Interconnect Structure for Network-on-Chips”, Proc. of the 

11 th Symp. On High Performance Interconnect, pp. 10-14, 2003 

A. Chakraborty and M. R. Greenstreet, “Efficient Self-Timed Interfaces for Crossing Clock Domains”, 

Proceedings of Ninth International Symposium on Asynchronous Circuits and Systems, pp. 78-88, May 2003. 

A. Edman and C. Svensson, "Timing Closure through a Globally Synchronous, Timing Partitioned Design 

Methodology", accepted for presentation at the 41 st Design Automation Conference, 2004.

Synchronous Latency Insensitive Design - ICS

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