Synchronous Latency Insensitive Design - ICS

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Introduction <strong>Synchronous</strong> design paradigm VERY established – we need to keep. (Easy to keep track on exact timing of all events; predictable performance) Vast experience used to manage ever increasing complexity. Critical: Timing relations between clock and data Present solution: “Flat” clock distribution (skew-free clock) Does not solve problem with data delays clk Balanced clk net - no skew Wire delay still affects data Christer Svensson, ASYNC 2004 4
Overview of wire properties Ground planes Twisted pair Cables Coaxial cable Microstrip Coplanar waveguide Circuit boards and chips We will concentrate on microstrip in the following Christer Svensson, ASYNC 2004 5
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3: Introduction The wire delay problem
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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