Synchronous Latency Insensitive Design - ICS

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Multiple clocks Can a multiple clock system be synchronous? Example – rationally related clocks f c1 f c2 =(2/3)f c1 f= <strong>Synchronous</strong> to f c1 Christer Svensson, ASYNC 2004 32
Multiple clocks FIFO synchronization can be extended to rationally related clocks (FIFO used for mitigation of delays and introduced clock jitter) Chakraborty 2003, (Our proposal 2004) Write pointer Read pointer Jitter accepted Chakraborty extended his scheme to any clock frequency relation Christer Svensson, ASYNC 2004 33
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 31: Synchronous Latency Insensitive Des
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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