Synchronous Latency Insensitive Design - ICS

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Overview of wire properties Capacity or maximum data rate RC-wire: Step response: S − 2T R w ( ) w C T = 1− e Eye opening of 64% yields S(T)=0.82 or T=0.85R w C w Max data rate LC-wire: Step response (skin effect): Max data rate, B 1 = T B = b = LC b RC A 2 L A 2 L S ( T ) = 1− erf ⎛ ⎜ ⎝ 2Z ρµ 0 w 0 L T ⎞ ⎟ ⎠ Christer Svensson, ASYNC 2004 10
Overview of wire properties Note the difference between latency and data rate RC case t d T s >t d (wave pipelining, Xu 2003) LC case t d T s
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9: Overview of wire properties Capacit
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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