Synchronous Latency Insensitive Design - ICS

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Synchronous Latency Insensitive Design System partition Design flow “Natural” partition (processors, memories, IP-blocks…) into isochronous regions Clock-true model & verification NEW: Insertion of dummy delays between isochronic regions. Clock-true verification. Synthesis & Back-end Replace dummy delays with elastic FIFO’s Timing verification Considerably easier, feedback can be avoided Christer Svensson, ASYNC 2004 26
Synchronous Latency Insensitive Design Implementation data reg reg data data strobe clk Example with three blocks and two links select Input counter strobe Output counter Local clock Synchronizing port Fixed nominal delay preset in counters Christer Svensson, ASYNC 2004 27
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 25: Synchronous Latency Insensitive Des
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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