Synchronous Latency Insensitive Design - ICS

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Outline • Introduction • Overview of wire properties • Architectural view of future systems • Synchronous Latency Insensitive Design • Multiple clocks • Conclusion Christer Svensson, ASYNC 2004 2
Introduction The wire delay problem was recognized very early (Anceau 1982) Wire delay ~ L 2 /s 2 , Gate delay ~s α , s=feature size, α=1..2 In spite of the “alarm” 1982, we still manage multigigahertz synchronous designs, BUT today with considerable problems. ASIC style designs normally limited to 300-500MHz clock, with severe “timing closure” problems. Multigigahertz designs very demanding full custom design style. Christer Svensson, ASYNC 2004 3
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