Synchronous Latency Insensitive Design - ICS

More documents

Recommendations

Info

Architectural view of future systems Chip On-chip global links Chip <strong>Synchronous</strong> blocks High speed board links Clock Christer Svensson, ASYNC 2004 18
Architectural view of future systems Chip On-chip global links Chip Challenges <strong>Synchronous</strong> blocks Allow scaling of clock rates and bandwidths Mitigate synchronization and clock skew problems Keep an unchanged synchronous High speed design paradigm board links Clock Christer Svensson, ASYNC 2004 19
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17: Overview of wire properties Upper w
Page 21 and 22: Architectural view of future system
Page 23 and 24: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?