Synchronous Latency Insensitive Design - ICS

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Overview of wire properties Estimated data-rates Top metal chip wire 10Gb/s @ 15mm Typical Board wire 10Gb/s @ 0.5m Low level metal wire 10Gb/s @ 1mm Low delay region Christer Svensson, ASYNC 2004 12
Overview of wire properties Low level on-chip wires Wire delay limits diameter of synchronous block System partition – “Global Asynchronous Local <strong>Synchronous</strong>” Upper on-chip wires Low delay, high data-rate global communication Inter-block communication Circuit board wires Can be used at least to 10Gb/s per wire Facilitates very high on-board bandwidths Christer Svensson, ASYNC 2004 13
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11: Overview of wire properties Note th
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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