Synchronous Latency Insensitive Design - ICS

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Synchronous Latency Insensitive Design Implementation example, receiver in 0.18µm CMOS f c =2.75GHz Area ≈ 3500 µm 2 Data sent over 2mm wire Latency 2 cycles Rx clk delay 1 cycle Rx input Tx clk Rx clk (SPICE circuit level @110 o C) Reference data Read data Christer Svensson, ASYNC 2004 30
Synchronous Latency Insensitive Design New method to ease timing closure in large DSM chips • Correct clock-true verification before synthesis • Synchronous design paradigm and design tools kept • Implementation induced data delays and clock skews mitigated • Implementation in standard libraries • Full clock alignment between blocks • No synchronizers, no risk for metastability Christer Svensson, ASYNC 2004 31
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 29: Synchronous Latency Insensitive Des
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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