Synchronous Latency Insensitive Design - ICS

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Overview of wire properties Upper wire/driver example Inverter in 0.18µm CMOS W n =88µm, w p =194µm, R S =20Ω Actual step response Step response without overdrive Step response, terminated 3.5µm 2µm Wire length 2cm 4µm 12µm 2µm x 4µm copper wire, low loss 12µm spacing, X-talk
Overview of wire properties Upper wire/driver example Estimated performance (length 2cm) • Simulated velocity: 10 8 m/s (c 0 /3) • Simulated maximum data-rate 10Gb/s • Each link is 16 bit wide, 2 links carry 320Gb/s (bidirectionally) • Each 2 links need 544µm width Christer Svensson, ASYNC 2004 17
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15: Overview of wire properties On-chip
Page 19 and 20: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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